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1. 发明授权

US06618230B2 Electrostatic discharge cell of integrated circuit 有权
公开(公告)号：US06618230B2
公开(公告)日：2003-09-09
申请号：US09909946
申请日：2001-07-23
申请人： Meng Huaug Liu , Chun-Hsiang Lai , Sing Su , Tao Cheng Lu
发明人： Meng Huaug Liu , Chun-Hsiang Lai , Sing Su , Tao Cheng Lu
IPC分类号： H02H900
CPC分类号： H01L27/0266
摘要： The present invention provides an IC ESD cell, which is applicable to multiple-power-input and mixed-voltage ICs and capable of maintaining power sequence independence of each power source. The ESD cell of the present invention comprises a voltage selector circuit, which connects two separate power sources to select the one having a higher potential as the output voltage. An NMOS is used to connect the two separate power sources. An RC circuit is connected to an output of the voltage selector circuit to distinguish ESD event from normal power source. Therefore, the channel of the NMOS will be conducted to let the ESD current be led out via a designed path, hence preventing internal circuits of an IC from damage and accomplishing the object of whole chip protection.

2. 发明授权

US06829125B2 ESD protection circuit for multi-power and mixed-voltage integrated circuit 有权
标题翻译：多功率和混合电压集成电路的ESD保护电路
公开(公告)号：US06829125B2
公开(公告)日：2004-12-07
申请号：US09938511
申请日：2001-08-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Sing Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Sing Su , Tao-Cheng Lu
IPC分类号： H02H900
CPC分类号： H01L27/0285
摘要： The invention discloses an ESD (Electro Static Discharge) protection circuit, including a resistor device, a capacitor device and a PMOS device. The resistor device is connected in series between a power supply and the capacitor device. The capacitor device is connected in series between the resistor device and the ground. A gate electrode of the PMOS device is connected between the resistor device and the capacitor device. A bulk electrode of the PMOS device is interconnected to a first electrode of the PMOS device, and the first electrode is connected to the power supply. Alternatively, another ESD protection circuit for multiple power supplies includes at least two aforementioned ESD protection circuits, and a common ESD bus. The ESD protection circuits are connected to separate power supplies, and both connected to the common ESD bus. By using the ESD protection circuit, there is no noise between the separate power supplies, and an ESD current could be discharged easily and safely.
摘要翻译：本发明公开了一种ESD（静电放电）保护电路，包括电阻器件，电容器器件和PMOS器件。电阻器件串联在电源和电容器之间。电容器器件串联在电阻器件和地之间。 PMOS器件的栅电极连接在电阻器件和电容器器件之间。 PMOS器件的体电极互连到PMOS器件的第一电极，并且第一电极连接到电源。或者，用于多个电源的另一ESD保护电路包括至少两个上述ESD保护电路和公共ESD总线。 ESD保护电路连接到单独的电源，并且都连接到公共ESD总线。通过使用ESD保护电路，在单独的电源之间不存在噪声，并且ESD电流可以容易且安全地放电。

3. 发明授权

US07573102B2 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US07573102B2
公开(公告)日：2009-08-11
申请号：US11496490
申请日：2006-08-01
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

4. 发明授权

US06965504B2 ESD protection apparatus and method for a high-voltage input pad 有权
标题翻译：高压输入板的ESD保护装置及方法
公开(公告)号：US06965504B2
公开(公告)日：2005-11-15
申请号：US10304137
申请日：2002-11-26
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
IPC分类号： H01L27/02 , H02H3/20
CPC分类号： H01L27/0266 , H01L27/0255
摘要： An ESD protection apparatus for a high-voltage input pad comprises a modulator connected between the input pad and a snapback device with first and second guard rings surrounding the modulator, third guard ring surrounding the snapback device, and first and second guard ring control circuits to control the guard rings such that the protection apparatus has higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.
摘要翻译：用于高电压输入焊盘的ESD保护装置包括连接在输入焊盘和回弹装置之间的调制器，其具有围绕调制器的第一和第二保护环，围绕着快速恢复装置的第三保护环，以及第一和第二保护环控制电路控制保护环，使保护装置在正常工作状态下具有较高的触发和保持电压，并在ESD事件下具有较低的触发和保持电压。

5. 发明授权

US07193274B2 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US07193274B2
公开(公告)日：2007-03-20
申请号：US10854792
申请日：2004-05-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

6. 发明申请

US20060273399A1 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
公开(公告)号：US20060273399A1
公开(公告)日：2006-12-07
申请号：US11496490
申请日：2006-08-01
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

7. 发明授权

US06661273B1 Substrate pump circuit and method for I/O ESD protection 有权
标题翻译：基板泵电路和I / O ESD保护方法
公开(公告)号：US06661273B1
公开(公告)日：2003-12-09
申请号：US10225160
申请日：2002-08-22
申请人： Chun-Hsiang Lai , Meng-Huang Liu , Shin Su , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Meng-Huang Liu , Shin Su , Tao-Cheng Lu
IPC分类号： H03K508
CPC分类号： H01L27/0277 , H03K5/08
摘要： A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.
摘要翻译：用于I / O ESD保护的衬底泵电路和方法，包括连接到I / O焊盘和内部电路之间的互连的NMOS指状包括连接到I / O焊盘和内部电路与衬底之间的互连的MOS器件在I / O焊盘处于ESD应力下时，在开关控制下将其导通以通过衬底电阻器进行泵浦电流，从而上升与NMOS指状物相邻的衬底的电位，从而减少的NMOS手指的触发电压。

8. 发明授权

US07291870B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US07291870B2
公开(公告)日：2007-11-06
申请号：US10904475
申请日：2004-11-12
申请人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266 , H01L29/7436 , H01L29/87
摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.
摘要翻译：耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

9. 发明授权

US07187527B2 Electrostatic discharge conduction device and mixed power integrated circuits using same 有权
标题翻译：静电放电传导器件和混合功率集成电路使用相同
公开(公告)号：US07187527B2
公开(公告)日：2007-03-06
申请号：US10933181
申请日：2004-09-02
申请人： Shin Su , Chun-Hsiang Lai , Cha-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Cha-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.
摘要翻译：用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。有源P环围绕具有与半导体衬底相同的导电类型的导电区域的晶体管的源极和漏极。耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

10. 发明授权

US06628488B2 Electrostatic discharge protection circuit 有权
公开(公告)号：US06628488B2
公开(公告)日：2003-09-30
申请号：US09874339
申请日：2001-06-06
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
IPC分类号： H02H900
CPC分类号： H01L27/0292 , H01L27/0251
摘要： An electrostatic discharge (ESD) protection circuit is disclosed. This invention relates an electrostatic discharge protection circuit for multi-power and mixed-voltage integrated circuit. In the electrostatic discharge protection circuit of the invention, an ESD protection cell formed with voltage selector, control circuit and transistor is used to connect with a independent power and ESD bus is used to connect with each ESD protection cell so that each power is isolated from each other during normal operation. Therefore, each power can be operated independently and circuit will be prevented from ESD during ESD discharging.

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