专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06834263B2 NROM structure 有权
标题翻译： NROM结构
公开(公告)号：US06834263B2
公开(公告)日：2004-12-21
申请号：US09815129
申请日：2001-03-22
申请人： Yao Wen Chang , Tao Cheng Lu , Wen Jer Tsai
发明人： Yao Wen Chang , Tao Cheng Lu , Wen Jer Tsai
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.
摘要翻译：可编程NROM的宏模型，用于在编程操作下模拟NROM的字符。当NROM被编程时，电荷被存储在氮化物材料层的一部分中以用于电荷俘获区域。正常MOS符号元件和短沟道MOS符号元件分别表示不具有电荷俘获区域的MOS和具有电荷俘获区域的MOS。此外，正常MOS符号元件与短沟道MOS符号元件串联，其中短沟道MOS符号元件的源极与正常MOS符号元件的漏极耦合。

2. 发明授权

US06320786B1 Method of controlling multi-state NROM 有权
标题翻译：控制多状态NROM的方法
公开(公告)号：US06320786B1
公开(公告)日：2001-11-20
申请号：US09777229
申请日：2001-02-05
申请人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
发明人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0466
摘要： A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed. On the other hand, if little current is detected, the second input voltage is adjusted to the third potential level. Similarly, if a high current is sensed, a third storage state is assumed. Conversely, when little current is detected, a fourth storage state is assumed.
摘要翻译：一种控制多状态NROM的方法。执行程序以注入被俘获在NROM的氮化物层内部的电荷。控制在氮化物层内捕获的电荷量，使得存储单元可以具有不同的阈值电压。为了从存储单元读取，向栅电极施加第一可变电压。根据施加到漏极端子的第二可变电压的范围，设置包括第一电位电平，第二电位电平和第三电位电平的从最小到最大的三个不同的电位电平。将第二输入电压调整到第一电位电平。当检测到高电流时，假设第一存储状态。如果检测到小的电流，则将第二输入电压调整到第二电位电平。当感测到高电流时，假设第二存储状态。另一方面，如果检测到小的电流，则将第二输入电压调整到第三电位电平。类似地，如果感测到高电流，则假设第三存储状态。相反，当检测到少量电流时，假设第四存储状态。

3. 发明授权

US07327611B2 Method and apparatus for operating charge trapping nonvolatile memory 有权
标题翻译：用于操作电荷捕获非易失性存储器的方法和装置
公开(公告)号：US07327611B2
公开(公告)日：2008-02-05
申请号：US11191367
申请日：2005-07-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/26
摘要： A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.
摘要翻译：具有电荷捕获结构的存储单元通过测量存储单元的衬底区域与存储单元的源极区域和存储器单元的漏极区域中的至少一个之间的电流来操作。当电荷捕获结构的其他部分存储不感兴趣的数据时，读取操作减小电荷俘获结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。通过增加存储单元上的净正电荷来擦除存储单元，并通过增加存储单元上的净负电荷进行编程。

4. 发明授权

US06721204B1 Memory erase method and device with optimal data retention for nonvolatile memory 有权
标题翻译：非易失性存储器的存储器擦除方法和具有最佳数据保留功能的器件
公开(公告)号：US06721204B1
公开(公告)日：2004-04-13
申请号：US10465395
申请日：2003-06-17
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1634
CPC分类号： G11C16/344
摘要： The invention advantageously provides a nonvolatile memory device and associated methods therefore, and, more particularly, an optimally designed nonvolatile memory device and methods therefor that advantageously prevent data loss in its trapping layer. A preferred embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate, erasing the memory cell, detrapping the memory cell, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value. For the detrapping step, electrons can be detrapped from the trapping layer to a channel region of the memory cell, or to a gate of the memory cell. The method according to the invention can further include the steps of verifying the state of the trapping layer (high or low), and repeating the erasing and detrapping steps if the state of the trapping layer is not verified.
摘要翻译：本发明有利地提供了一种非易失性存储器件和相关联的方法，更具体地说，是一种最佳设计的非易失性存储器件及其方法，有利于防止其捕获层中的数据丢失。用于操作根据本发明的非易失性存储器单元的方法的优选实施例有利地包括以下步骤：对存储单元进行编程，将电子从半导体衬底注入到存储器单元的陷阱层中，擦除存储单元，去除存储单元，并且重复擦除和去除步骤，直到存储器单元的阈值电压达到预定值。对于去除步骤，电子可以从捕获层去除到存储器单元的通道区域或存储单元的栅极。根据本发明的方法还可以包括以下步骤：如果未验证捕获层的状态，则验证捕获层的状态（高或低），并重复擦除和去除步骤。

5. 发明授权

US06215697B1 Multi-level memory cell device and method for self-converged programming 有权
标题翻译：用于自融合编程的多级存储单元器件和方法
公开(公告)号：US06215697B1
公开(公告)日：2001-04-10
申请号：US09231044
申请日：1999-01-14
申请人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
发明人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5625 , G11C2211/5634
摘要： A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell. The controller is also used to adjust voltages for both programming and read operations. The voltage difference resulting from the sources of the memory cell and reference cell is used to provide program control signals and thereby cease programming of the memory cell when convergence has been reached.
摘要翻译：一种用于自融合编程的多级存储单元设备和方法，其包括可切换地耦合到非可编程参考单元（或虚拟单元）的存储单元，所述单元布置在相应阵列中。电池的源节点和地之间的电流源电压与阈值电压相关，因此阈值电压增加，电流源电压降低。虚拟单元的阈值电压由稳定的电压源设定。对存储单元进行编程，并将存储单元的电流源电压与参考单元的电流源电压进行比较，因此可以使用电压差来检测编程单元的收敛与在参考细胞。参考单元和存储单元之间还包括控制器，用于根据浮动栅极存储单元的栅极耦合比来调整虚设单元的阈值电压。控制器也用于调节编程和读取操作的电压。由存储器单元和参考单元的源产生的电压差用于提供程序控制信号，从而在已经达到收敛时停止存储单元的编程。

6. 发明授权

US07529128B2 Integrated code and data flash memory 有权
标题翻译：集成代码和数据闪存
公开(公告)号：US07529128B2
公开(公告)日：2009-05-05
申请号：US11617613
申请日：2006-12-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
摘要翻译：用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

7. 发明授权

US07035147B2 Overerase protection of memory cells for nonvolatile memory 有权
标题翻译：对非易失性存储器的存储单元进行过度保护
公开(公告)号：US07035147B2
公开(公告)日：2006-04-25
申请号：US10465396
申请日：2003-06-17
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/344 , G11C16/0466 , G11C16/16 , G11C16/3445 , G11C16/3477
摘要： The invention provides a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a method for erasing a nonvolatile memory comprising a source, a gate, a drain, a channel and a trapping layer. The method according to a preferred embodiment of the invention generally comprises the steps of applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, applying a non-zero drain voltage to the drain in each erase shot wherein the drain voltage is generally higher in magnitude than the source voltage, generating hot holes in the nonvolatile memory, injecting the generated hot holes in the trapping layer near drain junction, and accordingly erasing the nonvolatile memory. The erase method according to a further embodiment of the invention comprises a verifying step after each erase shot for verifying the memory erase for the nonvolatile memory, and repeating the process steps according to the invention if the memory erase is not verified.
摘要翻译：本发明提供一种具有最佳存储器擦除功能的非易失性存储器和相应方法，更具体地说，涉及一种用于擦除包括源极，栅极，漏极，沟道和俘获层的非易失性存储器的方法。根据本发明的优选实施例的方法通常包括以下步骤：向栅极施加非零栅极电压，向源施加非零源电压，在每个擦除中向漏极施加非零漏极电压其中漏极电压的幅度通常大于源极电压，在非易失性存储器中产生热孔，在漏极结附近注入捕获层中产生的热孔，从而擦除非易失性存储器。根据本发明的另一实施例的擦除方法包括在用于验证非易失性存储器的存储器擦除的每个擦除镜头之后的验证步骤，并且如果未验证存储器擦除，则重复根据本发明的处理步骤。

8. 发明授权

US07486568B2 Method and apparatus for protection from over-erasing nonvolatile memory cells 有权
标题翻译：用于防止过度擦除非易失性存储单元的方法和装置
公开(公告)号：US07486568B2
公开(公告)日：2009-02-03
申请号：US11742398
申请日：2007-04-30
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/3404
摘要： Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.
摘要翻译：电荷捕获存储器单元被保护以响应于擦除命令而被过擦除。例如，响应于擦除命令，将一个偏置装置应用于编程电荷俘获存储器单元，并且施加另一个偏置布置以擦除电荷捕获存储器单元，使得电荷捕获存储器单元具有较高的净电荷，处于擦除状态，而不是编程状态。在另一示例中，具有电荷俘获存储器单元阵列的集成电路具有通过向电荷捕获存储器单元施加相似的偏置布置来响应擦除命令的逻辑。在另一实例中，制造这种集成电路。

9. 发明授权

US07132350B2 Method for manufacturing a programmable eraseless memory 有权
标题翻译：制造可编程擦除存储器的方法
公开(公告)号：US07132350B2
公开(公告)日：2006-11-07
申请号：US10641897
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

10. 发明授权

US07057938B2 Nonvolatile memory cell and operating method 有权
标题翻译：非易失性存储单元和操作方法
公开(公告)号：US07057938B2
公开(公告)日：2006-06-06
申请号：US10756777
申请日：2004-01-14
申请人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit. The present invention also provides a method for sensing and reading at least one bit in a nonvolatile memory comprising applying a bias voltage to the memory, detecting a threshold voltage or read current, comparing the threshold voltage with a reference voltage or comparing the read current with a reference current, and identifying the at least one bit as erased or programmed.
摘要翻译：本发明的一个实施例提供一种具有非易失性存储器的系统，其包括ap型半导体衬底，p型半导体衬底上的氧化物层，氧化物层上方的氮化物层，氮化物层上的附加氧化物层，分别形成在两个N +结中的源极和漏极，非易失性存储器中的第一位和第二位，以及相应地至少两个操作状态（即擦除）的附加氧化物层，p型半导体层中的两个N +结，和程序）。也就是说，非易失性存储器中的一位可以处于擦除状态或程序状态。为了擦除一点，电子注入非易失性存储器的栅极。为了编程一点，注入电孔或减少电子的位。本发明还提供了一种用于感测和读取非易失性存储器中的至少一个位的方法，包括向存储器施加偏置电压，检测阈值电压或读取电流，将阈值电压与参考电压进行比较，或将读取的电流与参考电流，并将所述至少一个位识别为擦除或编程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式