专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06834263B2 NROM structure 有权
标题翻译： NROM结构
公开(公告)号：US06834263B2
公开(公告)日：2004-12-21
申请号：US09815129
申请日：2001-03-22
申请人： Yao Wen Chang , Tao Cheng Lu , Wen Jer Tsai
发明人： Yao Wen Chang , Tao Cheng Lu , Wen Jer Tsai
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.
摘要翻译：可编程NROM的宏模型，用于在编程操作下模拟NROM的字符。当NROM被编程时，电荷被存储在氮化物材料层的一部分中以用于电荷俘获区域。正常MOS符号元件和短沟道MOS符号元件分别表示不具有电荷俘获区域的MOS和具有电荷俘获区域的MOS。此外，正常MOS符号元件与短沟道MOS符号元件串联，其中短沟道MOS符号元件的源极与正常MOS符号元件的漏极耦合。

2. 发明授权

US06320786B1 Method of controlling multi-state NROM 有权
标题翻译：控制多状态NROM的方法
公开(公告)号：US06320786B1
公开(公告)日：2001-11-20
申请号：US09777229
申请日：2001-02-05
申请人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
发明人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0466
摘要： A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed. On the other hand, if little current is detected, the second input voltage is adjusted to the third potential level. Similarly, if a high current is sensed, a third storage state is assumed. Conversely, when little current is detected, a fourth storage state is assumed.
摘要翻译：一种控制多状态NROM的方法。执行程序以注入被俘获在NROM的氮化物层内部的电荷。控制在氮化物层内捕获的电荷量，使得存储单元可以具有不同的阈值电压。为了从存储单元读取，向栅电极施加第一可变电压。根据施加到漏极端子的第二可变电压的范围，设置包括第一电位电平，第二电位电平和第三电位电平的从最小到最大的三个不同的电位电平。将第二输入电压调整到第一电位电平。当检测到高电流时，假设第一存储状态。如果检测到小的电流，则将第二输入电压调整到第二电位电平。当感测到高电流时，假设第二存储状态。另一方面，如果检测到小的电流，则将第二输入电压调整到第三电位电平。类似地，如果感测到高电流，则假设第三存储状态。相反，当检测到少量电流时，假设第四存储状态。

3. 发明授权

US08501591B2 Method for manufacturing a multiple-bit-per-cell memory 有权
标题翻译：制造多位单元存储器的方法
公开(公告)号：US08501591B2
公开(公告)日：2013-08-06
申请号：US11285614
申请日：2005-11-21
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

4. 发明授权

US06996011B2 NAND-type non-volatile memory cell and method for operating same 有权
标题翻译： NAND型非易失性存储单元及其操作方法
公开(公告)号：US06996011B2
公开(公告)日：2006-02-07
申请号：US10855286
申请日：2004-05-26
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , H01L27/115
摘要： A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.
摘要翻译：由多个基本相同的EEPROM单元形成的NAND型可擦除可编程只读存储器（EEPROM）器件，每个EEPROM单元能够存储两位信息。用于操作存储器的简单方法包括擦除，编程和读取设备。

5. 发明授权

US07327611B2 Method and apparatus for operating charge trapping nonvolatile memory 有权
标题翻译：用于操作电荷捕获非易失性存储器的方法和装置
公开(公告)号：US07327611B2
公开(公告)日：2008-02-05
申请号：US11191367
申请日：2005-07-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/26
摘要： A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.
摘要翻译：具有电荷捕获结构的存储单元通过测量存储单元的衬底区域与存储单元的源极区域和存储器单元的漏极区域中的至少一个之间的电流来操作。当电荷捕获结构的其他部分存储不感兴趣的数据时，读取操作减小电荷俘获结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。通过增加存储单元上的净正电荷来擦除存储单元，并通过增加存储单元上的净负电荷进行编程。

6. 发明授权

US06721204B1 Memory erase method and device with optimal data retention for nonvolatile memory 有权
标题翻译：非易失性存储器的存储器擦除方法和具有最佳数据保留功能的器件
公开(公告)号：US06721204B1
公开(公告)日：2004-04-13
申请号：US10465395
申请日：2003-06-17
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1634
CPC分类号： G11C16/344
摘要： The invention advantageously provides a nonvolatile memory device and associated methods therefore, and, more particularly, an optimally designed nonvolatile memory device and methods therefor that advantageously prevent data loss in its trapping layer. A preferred embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate, erasing the memory cell, detrapping the memory cell, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value. For the detrapping step, electrons can be detrapped from the trapping layer to a channel region of the memory cell, or to a gate of the memory cell. The method according to the invention can further include the steps of verifying the state of the trapping layer (high or low), and repeating the erasing and detrapping steps if the state of the trapping layer is not verified.
摘要翻译：本发明有利地提供了一种非易失性存储器件和相关联的方法，更具体地说，是一种最佳设计的非易失性存储器件及其方法，有利于防止其捕获层中的数据丢失。用于操作根据本发明的非易失性存储器单元的方法的优选实施例有利地包括以下步骤：对存储单元进行编程，将电子从半导体衬底注入到存储器单元的陷阱层中，擦除存储单元，去除存储单元，并且重复擦除和去除步骤，直到存储器单元的阈值电压达到预定值。对于去除步骤，电子可以从捕获层去除到存储器单元的通道区域或存储单元的栅极。根据本发明的方法还可以包括以下步骤：如果未验证捕获层的状态，则验证捕获层的状态（高或低），并重复擦除和去除步骤。

7. 发明授权

US06215697B1 Multi-level memory cell device and method for self-converged programming 有权
标题翻译：用于自融合编程的多级存储单元器件和方法
公开(公告)号：US06215697B1
公开(公告)日：2001-04-10
申请号：US09231044
申请日：1999-01-14
申请人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
发明人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5625 , G11C2211/5634
摘要： A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell. The controller is also used to adjust voltages for both programming and read operations. The voltage difference resulting from the sources of the memory cell and reference cell is used to provide program control signals and thereby cease programming of the memory cell when convergence has been reached.
摘要翻译：一种用于自融合编程的多级存储单元设备和方法，其包括可切换地耦合到非可编程参考单元（或虚拟单元）的存储单元，所述单元布置在相应阵列中。电池的源节点和地之间的电流源电压与阈值电压相关，因此阈值电压增加，电流源电压降低。虚拟单元的阈值电压由稳定的电压源设定。对存储单元进行编程，并将存储单元的电流源电压与参考单元的电流源电压进行比较，因此可以使用电压差来检测编程单元的收敛与在参考细胞。参考单元和存储单元之间还包括控制器，用于根据浮动栅极存储单元的栅极耦合比来调整虚设单元的阈值电压。控制器也用于调节编程和读取操作的电压。由存储器单元和参考单元的源产生的电压差用于提供程序控制信号，从而在已经达到收敛时停止存储单元的编程。

8. 发明授权

US07307888B2 Method and apparatus for operating nonvolatile memory in a parallel arrangement 有权
标题翻译：以并行方式操作非易失性存储器的方法和装置
公开(公告)号：US07307888B2
公开(公告)日：2007-12-11
申请号：US11191329
申请日：2005-07-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475
摘要： A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.
摘要翻译：具有电荷存储结构的存储单元通过测量存储单元的衬底区域和存储单元的一个载流节点之间的电流来读取。当电荷存储结构的其他部分存储不感兴趣的数据时，读取操作减小了电荷存储结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。示例性布置是单个存储器单元，列或NOR连接的存储器单元，以及存储器单元的虚拟接地阵列。

9. 发明授权

US07187590B2 Method and system for self-convergent erase in charge trapping memory cells 有权
标题翻译：电荷捕获存储器单元中自会聚擦除的方法和系统
公开(公告)号：US07187590B2
公开(公告)日：2007-03-06
申请号：US10876255
申请日：2004-06-24
申请人： Nian-Kai Zous , Wen-Jer Tsai , Hung-Yueh Chen , Tao Cheng Lu
发明人： Nian-Kai Zous , Wen-Jer Tsai , Hung-Yueh Chen , Tao Cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , H01L29/7885 , H01L29/792
摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.
摘要翻译：提供了用于操作电荷捕获存储器单元的过程和存储器架构。用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。从而避免了过度擦除的情况。

10. 发明授权

US07158411B2 Integrated code and data flash memory 有权
标题翻译：集成代码和数据闪存
公开(公告)号：US07158411B2
公开(公告)日：2007-01-02
申请号：US10815370
申请日：2004-04-01
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
摘要翻译：用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式