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91. 发明申请

US20090150748A1 Data Storage and Replay Apparatus 有权
标题翻译：数据存储和重放设备
公开(公告)号：US20090150748A1
公开(公告)日：2009-06-11
申请号：US11573192
申请日：2005-07-22
申请人： Sebastian Egner , Nicolaas Lambert , Ludovicus M. G. M. Tolhuizen , Victor M. G. Van Acht , Martinus W. Blum
发明人： Sebastian Egner , Nicolaas Lambert , Ludovicus M. G. M. Tolhuizen , Victor M. G. Van Acht , Martinus W. Blum
IPC分类号： G06F11/10
CPC分类号： G06F11/1012 , G06F11/1068 , G11B20/1816 , G11B20/1833 , H03M13/35
摘要： A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given said information. In this way the speed of transmission of data to the device can be maximized while keeping the error rate below an acceptable level in the predicted future after decoding. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.
摘要翻译：数据存储和重放设备使用存储介质（通常为闪速存储器电路）性能演变的测量来预测从存储介质的区域检索的错误率。该预测用作在存储数据之前动态选择用于对数据进行编码的ECC的基础。从多个可用ECC中选择ECC，使得选择最快的可编码ECC，其被预测产生不超过给定所述信息的预定后解码错误率。以这种方式，可以最大化数据传输到设备的速度，同时在解码之后将误差率保持在预测未来的可接受水平。在对通常是音频或视频数据的数据进行解码时，以预定速度进行解码和重放。在另一个实施例中，动态地选择使用多个ECC一起存储的数据和ECC，以进行解码，从而可以最大化输出数据速率或者可以最小化重播的功耗。

92. 发明申请

US20090129190A1 DRIVING A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS 有权
标题翻译：驱动电阻HYSTERESIS元件的记忆矩阵
公开(公告)号：US20090129190A1
公开(公告)日：2009-05-21
申请号：US11817715
申请日：2006-02-28
申请人： Teunis Jian Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jian Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C7/00 , G11C11/416 , G11C8/00 , G11C5/14
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。在所选行中的列端子和单元（20）的行端子之间施加电压差，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差被施加在所选列的单元（20）的列端子和行端子之间，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

93. 发明申请

US20090122590A1 CONTROL OF A MEMORY MATRIX WITH RESISTANCE HYSTERESIS ELEMENTS 有权
标题翻译：具有电阻HYSTERESIS元件的记忆矩阵的控制
公开(公告)号：US20090122590A1
公开(公告)日：2009-05-14
申请号：US11817754
申请日：2006-03-03
申请人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

94. 发明申请

US20090072212A1 ANTI-FUSE MEMORY DEVICE 有权
标题翻译：防静电存储器件
公开(公告)号：US20090072212A1
公开(公告)日：2009-03-19
申请号：US11914662
申请日：2006-05-04
申请人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M.G. Van Acht , Nicolaas Lambert
发明人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.
摘要翻译：一次性可编程（OTP）存储器单元（10），包括涂覆有第二导电稳定过渡化合物（14）的第一金属层（12），其间具有绝缘层（16）。第一层和第二层（12,14）根据它们之间的吉布斯自由能的差异来选择，这决定了由于两种材料之间的放热化学反应而产生的化学能。第一层和第二层（12,14）的材料本身是高度热稳定的，但是当向单元（10）施加电压时，导致绝缘层（16）的局部击穿产生热点（18 ），其在第一和第二层（12,14）之间引起放热化学反应。放热反应产生足够的热量（20）以在电池上产生短路并因此降低其电阻。

95. 发明申请

US20080279025A1 Electronic Circuit with Memory for Which a Threshold Level is Selected 审中-公开
标题翻译：具有选择阈值电平的具有存储器的电子电路
公开(公告)号：US20080279025A1
公开(公告)日：2008-11-13
申请号：US11568003
申请日：2005-04-21
申请人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
发明人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
IPC分类号： G11C7/02 , H03M7/00
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

96. 发明申请

US20080270681A1 Non-Volatile Memory with Block Erasable Locations 有权
标题翻译：具有块可擦除位置的非易失性存储器
公开(公告)号：US20080270681A1
公开(公告)日：2008-10-30
申请号：US12158978
申请日：2006-12-13
申请人： Victor M.G. Van Acht , Nicolaas Lambert
发明人： Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： A main memory (10) comprises a plurality of physical blocks of memory locations. The main memory (10) supports erasing of at least a physical block at a time. Pointer information is stored in a subset (40, 42) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block (40) in the subset (40, 42). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block (42) of the subset (40, 42) at least after the first block (40) has been filled. The first block (40) is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset (40, 42) contains a most recent version of the pointing information.
摘要翻译：主存储器（10）包括存储器位置的多个物理块。主存储器（10）一次支持擦除至少一个物理块。指针信息被存储在块的子集（40,42）中，用于标识被分配给各个功能的各个物理块。指向信息的连续版本存储在最初在子集（40,42）中的第一块（40）中的彼此不同的存储器位置处。至少在第一块（40）已被填充之后，比连续版本更新的指向信息的后续版本被存储在子集（40,42）的第二块（42）中。第一块（40）在存储后续版本之后被擦除。在主存储器的启动时，通过测试子集（40,42）中的哪个块包含指向信息的最新版本来恢复指向信息。

97. 发明申请

US20080252338A1 Single Threshold and Single Conductivity Type Amplifier/Buffer 有权
标题翻译：单阈值和单电导型放大器/缓冲器
公开(公告)号：US20080252338A1
公开(公告)日：2008-10-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K3/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

98. 发明授权

US07358854B2 Method and device to identify a periodic light source 失效
标题翻译：识别周期性光源的方法和装置
公开(公告)号：US07358854B2
公开(公告)日：2008-04-15
申请号：US10511364
申请日：2003-04-01
申请人： Sebastian Egner , Nicolaas Lambert , Kero Van Gelder
发明人： Sebastian Egner , Nicolaas Lambert , Kero Van Gelder
IPC分类号： G08B1/08 , G08B13/14 , G08B21/00 , G08B5/22 , H04B10/00
CPC分类号： G01S3/783 , G01S5/0252 , G01S7/4804
摘要： In a device for location positioning, and more particularly, in a system for identifying an environmental source emitting a base frequency and waveform signal, a sensor (101) records an environmental source (105) emitting a base frequency and waveform signal, the signal being amplified (102), digitized (103), processed and compared (104) with a stored unique waveform characteristic. On the basis of the comparison result(s), location positioning and/or a device orientation may be determined.
摘要翻译：更具体地，在用于识别发射基频和波形信号的环境源的系统中，传感器（101）记录发射基频和波形信号的环境源（105），信号为放大（102），数字化（103），处理和比较（104）与存储的唯一波形特性。基于比较结果，可以确定位置定位和/或设备取向。

99. 发明申请

US20060053268A1 Storing bios in persistent system memory 审中-公开
标题翻译：将bios存储在持久性系统内存中
公开(公告)号：US20060053268A1
公开(公告)日：2006-03-09
申请号：US10533752
申请日：2003-10-08
申请人： Wihelmus Franciscus Fontijn , Nicolaas Lambert , Robert Jochemsen , Adrianus Denissen
发明人： Wihelmus Franciscus Fontijn , Nicolaas Lambert , Robert Jochemsen , Adrianus Denissen
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/4401
摘要： When booting a personal computer, it needs to find instructions immediately to tell it what to run to start up the personal computer. These it finds within the so-called basic input/output system (BIOS) program. Usually the BIOS program is stored in a separate location, for example a ROM. It is usually shadowed into system memory (SM) to speed up its operation. The copying of the BIOS program to system memory (SM), amongst others, causes the boot process to be a relatively slow process. In the present invention, the system memory (SM) comprises a persistent system memory (PSM) and the BIOS program is stored in the persistent system memory (PSM). Furthermore, selected information used by the BIOS program is stored in persistent system memory (PSM) as well. As a result, the speed of booting the personal computer is significantly increased.
摘要翻译：引导个人电脑时，需要立即找到指示，告诉您运行什么来启动个人电脑。它们在所谓的基本输入/输出系统（BIOS）程序中找到。通常BIOS程序存储在单独的位置，例如ROM。它通常被遮蔽到系统存储器（SM）中以加速其操作。将BIOS程序复制到系统存储器（SM）等，导致引导过程是一个相对较慢的过程。在本发明中，系统存储器（SM）包括持久系统存储器（PSM），并且BIOS程序存储在持久系统存储器（PSM）中。此外，BIOS程序使用的所选信息也存储在持久系统存储器（PSM）中。因此，引导个人计算机的速度显着增加。

100. 发明申请

US20050132251A1 Method for handling data, data storage system, file system and computer program product 审中-公开
标题翻译：处理数据，数据存储系统，文件系统和计算机程序产品的方法
公开(公告)号：US20050132251A1
公开(公告)日：2005-06-16
申请号：US10502525
申请日：2002-12-23
申请人： Adrianus Denissen , Robert Jochemsen , Nicolaas Lambert , Hong Li , Albert Rijkaert , Rudi Wijnands
发明人： Adrianus Denissen , Robert Jochemsen , Nicolaas Lambert , Hong Li , Albert Rijkaert , Rudi Wijnands
IPC分类号： G06F3/06 , G06F11/00 , G06F17/30 , G11B20/10 , G11B20/12
CPC分类号： G06F16/10
摘要： In a file system and in particular in a real-time file system it might not be possible to write a data to disc completely. Nevertheless the data that has been written to disc is often still useful, for example in case of an MPEG-stream. Marking parts of the file defective in the file system providing meta-data enables an application to perform application specific error correction or error concealment By using a filter driver, the file system can be extended with this error handling, thus making this functionality available to every application.
摘要翻译：在文件系统中，特别是在实时文件系统中，可能无法将数据完全写入光盘。然而，已写入光盘的数据通常仍然有用，例如在MPEG流的情况下。在提供元数据的文件系统中标记文件有缺陷的部分使应用程序能够执行应用程序特定的错误纠正或错误隐藏通过使用过滤器驱动程序，可以通过此错误处理扩展文件系统，从而使此功能可用于每个应用。

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