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    • 3. 发明申请
    • CIRCUIT WITH A MEMORY ARRAY AND A REFERENCE LEVEL GENERATOR CIRCUIT
    • 具有存储器阵列的电路和参考电平发生器电路
    • US20100103751A1
    • 2010-04-29
    • US11813862
    • 2006-01-05
    • Victor M G Van AchtNicolaas LambertPierre H. Woerlee
    • Victor M G Van AchtNicolaas LambertPierre H. Woerlee
    • G11C7/06G11C5/14G11C7/02
    • G11C7/14
    • A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.
    • 电路包括存储器单元阵列(10)。 多个感测电路(20)耦合到相应存储单元(10)的输出(14),用于将存储单元(10)中的相应一个的输出信号与参考信号进行比较以形成数据信号 来自存储单元(10)中的相应一个的输出信号。 参考发生器电路(24,26)从一个和形成参考信号,其中寻址组的每个存储单元(10)中的每个相应的一个贡献作为存储单元的相应一个的输出信号的函数 (10)。 在超过参考信号的饱和距离上的输出信号值的贡献相等,并且在超过参考信号以下的饱和距离处的输出信号值的贡献相等。 在单元格中存储多级数据的情况下,从基准电平以上和低于基准电平的中心电平到饱和电平的距离是相互不同的,其比率对应于已经被编程的单元计数的比率 各级别。
    • 6. 发明授权
    • Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers
    • 具有使用SiGe间隔物的具有LDD结构的MOS晶体管的半导体器件的制造
    • US06255183B1
    • 2001-07-03
    • US09064207
    • 1998-04-22
    • Jurriaan SchmitzYouri V. PonomarevPierre H. Woerlee
    • Jurriaan SchmitzYouri V. PonomarevPierre H. Woerlee
    • H01L21336
    • H01L29/6659H01L21/2254H01L21/28247H01L21/823864H01L29/665Y10S438/923
    • A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si1-xGex, 0.1
    • 一种制造具有LDD结构的MOS晶体管的半导体器件的方法。 在硅衬底(1)的表面(5)上形成栅电介质(6)和栅电极(7,8)。 然后暴露与栅电极相邻的表面,并且在与栅电极相邻的表面的边缘(9)上形成一层半导体材料(10)。 随后,栅极电极和半导体材料层用作掩模,随后引入离子(13,14)。 最后,进行热处理,由此通过激活注入的离子并且通过从半导体材料层扩散掺杂剂的原子而形成源极区(16,17)和漏极区(18,19)。 这些由扩散形成的这些区域的部分(b)在这里是弱掺杂的,位于通过激活注入的离子和沟道区(20,21)形成的更强的掺杂部分(a)之间。 因此形成了LDD结构。 在该方法中,在与栅电极相邻的边缘上设置由Si1-xGex形成的半导体材料层,0.1
    • 9. 发明授权
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US06368915B1
    • 2002-04-09
    • US09527203
    • 2000-03-16
    • Andreas H. MontreeJurriaan SchmitzPierre H. Woerlee
    • Andreas H. MontreeJurriaan SchmitzPierre H. Woerlee
    • H01L21336
    • H01L21/28273H01L29/42324H01L29/66825
    • In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region 4 of a first conductivity type is defined at a surface 2 of a semiconductor body 1, and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. Then, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer 14. In this recess a first insulating layer is applied providing a floating gate dielectric 19, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer 14, which first conductive layer is shaped into a floating gate 21 by means of masked etching. The floating gate 21 has a substantially flat surface portion 22 extending substantially parallel to the surface 2 of the semiconductor body 1 and sidewall portions 23 extending substantially perpendicularly to the surface 2 of the semiconductor body 1. In a next step, the floating gate 21 is covered with a second insulating layer providing an inter-gate dielectric 25, to which second insulating layer a second conductive layer is applied, which is shaped into an overlapping control gate 27. The control gate 27 is capacitively coupled to the substantially flat surface portion 22 of the floating gate 21 and to at least the sidewall portions 23 of the floating gate 21 situated adjacent to the source zone 11 and the drain zone 12 of the memory element.
    • 在制造包括非易失性存储元件的半导体器件的方法中,第一导电类型的有源区4限定在半导体本体1的表面2,并且施加图案化层,该图案层用作 在半导体本体1中形成第二导电类型的源极区11和漏极区12期间形成掩模。然后,提供足够大以覆盖图案化层的厚度的电介质层14,该电介质层14 通过材料去除处理去除其厚度的一部分,直到图案化层被暴露,去除图案层,从而在电介质层14中形成凹陷。在该凹槽中,施加第一绝缘层,提供浮动栅极 电介质19,第一绝缘层施加第一导电层,填充介电层14中的凹部,该第一导电层被成形为浮动栅极21 通过掩模蚀刻。 浮动栅极21具有基本上平行于半导体本体1的表面2延伸的基本上平坦的表面部分22,以及基本上垂直于半导体本体1的表面2延伸的侧壁部分23.在下一步骤中,浮动栅极21是 覆盖有提供栅极间电介质25的第二绝缘层,施加第二绝缘层的第二导电层被成形为重叠的控制栅极27.控制栅极27电容耦合到基本平坦的表面部分22 和至少位于与存储元件的源极区11和漏极区12相邻的浮动栅极21的侧壁部分23。
    • 10. 发明授权
    • Semiconductor device provided having a programmable element with a
high-conductivity buried contact region
    • 提供具有可编程元件的半导体器件具有高导电性掩埋接触区域
    • US5502326A
    • 1996-03-26
    • US381002
    • 1995-01-25
    • Jan W. SlotboomPierre H. WoerleeReinout Woltjer
    • Jan W. SlotboomPierre H. WoerleeReinout Woltjer
    • H01L27/10G11C17/16H01L21/8246H01L23/525H01L27/102H01L27/112H01L29/00H01L27/095
    • G11C17/16H01L23/5252H01L2924/0002Y10S257/91
    • A semiconductor device includes a programmable element having a doped semiconductor region (4) and a conductor region (6) which are separated from one another by at least a portion of an insulating layer (5). The conductor region (6) is of a material suitable for forming a rectifying junction (8) with the material of the semiconductor region (4). To achieve a comparatively high conductivity connection to the semiconductor region (4), the element is further provided with a contact region (3) which has a comparatively low electrical resistance compared with the semiconductor region (4). The contact region (3) is provided at a side of the semiconductor region (4) remote from the insulating layer (5) and is separated from the insulating layer (5) by the semiconductor region (4). Both the semiconductor region (4) and the contact region (5) are laterally bounded by an isolating region (7) at opposing sides. The invention thus offers a device provided with a programmable element of a substantially more compact structure than a comparable conventional programmable element.
    • 半导体器件包括具有掺杂半导体区域(4)的可编程元件和通过绝缘层(5)的至少一部分彼此分离的导体区域(6)。 导体区域(6)是适于与半导体区域(4)的材料形成整流结(8)的材料。 为了实现与半导体区域(4)的较高的导电性连接,元件还具有与半导体区域(4)相比具有相对低的电阻的接触区域(3)。 接触区域(3)设置在远离绝缘层(5)的半导体区域(4)的一侧,并且通过半导体区域(4)与绝缘层(5)分离。 半导体区域(4)和接触区域(5)都由相对侧的隔离区域(7)横向界定。 因此,本发明提供了一种具有比可比较的常规可编程元件基本上更紧凑结构的可编程元件的装置。