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1. 发明申请

US20080316805A1 Electronic Circuit With a Memory Matrix 有权
标题翻译：具有存储矩阵的电子电路
公开(公告)号：US20080316805A1
公开(公告)日：2008-12-25
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储器单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是具有耦合到存储单元（16）的行的第一行导体（10）的控制电极的垂直晶体管，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在存储器单元所属的行对之间的节点（166）和第二行导体（12）之间。

2. 发明授权

US07679952B2 Electronic circuit with a memory matrix 有权
标题翻译：具有记忆矩阵的电子电路
公开(公告)号：US07679952B2
公开(公告)日：2010-03-16
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.
摘要翻译：在示例实施例中，电子电路包括具有存储器单元的行和列的存储器矩阵。为每行提供第一行导体。第二行导体对应于行对，每个连续的行与前面的行之一形成相应的对，使得每一对与下一对的一行重叠。为每个列提供列导体。每个存储单元包括存取晶体管，节点和第一和第二电阻存储器元件。存取晶体管具有耦合到存储单元行的第一行导体的控制电极，耦合在存储单元的列的列导体和节点之间的主电流通道。第一和第二电阻性存储器元件耦合在该存储器单元所属的行对之间的节点和第二行导体之间。

3. 发明申请

US20080258770A1 Single Threshold and Single Conductivity Type Logic 有权
标题翻译：单阈值和单电导型逻辑
公开(公告)号：US20080258770A1
公开(公告)日：2008-10-23
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主要的当前裸片耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

4. 发明授权

US07834668B2 Single threshold and single conductivity type amplifier/buffer 有权
标题翻译：单阈值和单导电型放大器/缓冲器
公开(公告)号：US07834668B2
公开(公告)日：2010-11-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03B1/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

5. 发明授权

US07671660B2 Single threshold and single conductivity type logic 有权
标题翻译：单阈值和单导电类型逻辑
公开(公告)号：US07671660B2
公开(公告)日：2010-03-02
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K17/16
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主电流路径耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

6. 发明申请

US20080252338A1 Single Threshold and Single Conductivity Type Amplifier/Buffer 有权
标题翻译：单阈值和单电导型放大器/缓冲器
公开(公告)号：US20080252338A1
公开(公告)日：2008-10-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K3/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

7. 发明授权

US07923813B2 Anti-fuse memory device 有权
标题翻译：防熔丝存储器件
公开(公告)号：US07923813B2
公开(公告)日：2011-04-12
申请号：US11914662
申请日：2006-05-04
申请人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M. G Van Acht , Nicolaas Lambert
发明人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M. G Van Acht , Nicolaas Lambert
IPC分类号： H01L23/52 , H01L21/70
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.
摘要翻译：一次性可编程（OTP）存储器单元（10），包括涂覆有第二导电稳定过渡化合物（14）的第一金属层（12），其间具有绝缘层（16）。第一层和第二层（12,14）根据它们之间的吉布斯自由能的差异来选择，这决定了由于两种材料之间的放热化学反应而产生的化学能。第一层和第二层（12,14）的材料本身是高度热稳定的，但是当向单元（10）施加电压时，导致绝缘层（16）的局部击穿产生热点（18 ），其在第一和第二层（12,14）之间引起放热化学反应。放热反应产生足够的热量（20）以在电池上产生短路并因此降低其电阻。

8. 发明申请

US20090072212A1 ANTI-FUSE MEMORY DEVICE 有权
标题翻译：防静电存储器件
公开(公告)号：US20090072212A1
公开(公告)日：2009-03-19
申请号：US11914662
申请日：2006-05-04
申请人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M.G. Van Acht , Nicolaas Lambert
发明人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.
摘要翻译：一次性可编程（OTP）存储器单元（10），包括涂覆有第二导电稳定过渡化合物（14）的第一金属层（12），其间具有绝缘层（16）。第一层和第二层（12,14）根据它们之间的吉布斯自由能的差异来选择，这决定了由于两种材料之间的放热化学反应而产生的化学能。第一层和第二层（12,14）的材料本身是高度热稳定的，但是当向单元（10）施加电压时，导致绝缘层（16）的局部击穿产生热点（18 ），其在第一和第二层（12,14）之间引起放热化学反应。放热反应产生足够的热量（20）以在电池上产生短路并因此降低其电阻。

9. 发明授权

US07706234B2 Optical head with switchable diameter of the radiation spot on the radiation detector 失效
标题翻译：光头具有辐射探测器上辐射点的可切换直径
公开(公告)号：US07706234B2
公开(公告)日：2010-04-27
申请号：US11718921
申请日：2005-11-11
申请人： Andrei Mijiritskii , Sjoerd Stallinga , Bernardus Hendrikus Wilhelmus Hendriks , Stein Kuiper , Albert Hendrik Jan Immink , Teunis Willem Tukker , Coen Theodorus Hubertus Fran Liedenbaum
发明人： Andrei Mijiritskii , Sjoerd Stallinga , Bernardus Hendrikus Wilhelmus Hendriks , Stein Kuiper , Albert Hendrik Jan Immink , Teunis Willem Tukker , Coen Theodorus Hubertus Fran Liedenbaum
IPC分类号： G11B7/00
CPC分类号： G11B7/1353 , G02B3/14 , G02B26/005 , G11B7/1369 , G11B7/1378
摘要： In an optical scanning device (10) capable of scanning an information plane of an optical record carrier (5) of different types such as BD, DVD and CD, the diameter of the radiation spot on the detector (7) is dependent on the numerical aperture of the objective system (4) that is used for scanning the record carrier An optimal design of the optical detection system for scanning a BD, result in a small radiation spot for the other types such as DVD and CD. By implementing an optical element (13) that increases the diameter of the radiation spot in the situation a DVD or CD is scanned, the influence of stray light is reduced and the tracking signals are improved
摘要翻译：在能够扫描诸如BD，DVD和CD的不同类型的光学记录载体（5）的信息平面的光学扫描装置（10）中，检测器（7）上的辐射点的直径取决于数字用于扫描记录载体的物镜系统（4）的孔径用于扫描BD的光学检测系统的最佳设计导致诸如DVD和CD的其它类型的小的辐射点。通过实现在DVD或CD被扫描的情况下增加辐射点的直径的光学元件（13），杂散光的影响减小并且跟踪信号得到改善

10. 发明申请

US20080285416A1 Method for Multilevel Recording Information on a Record Carrier a Record Carrier and a Recording Device 审中-公开
标题翻译：用于记录载体上记录载体和记录装置的多级记录信息的方法
公开(公告)号：US20080285416A1
公开(公告)日：2008-11-20
申请号：US11571538
申请日：2005-06-23
申请人： Erwin Rinaldo Meinders , Andrei Mijiritskii
发明人： Erwin Rinaldo Meinders , Andrei Mijiritskii
IPC分类号： G11B7/00
CPC分类号： G11B7/00455
摘要： A record carrier comprises three layers that react with each other when irradiated to form a mark on the record carrier. The three layers are separated by a two separating layers that prevent direct contact of the three layers thus providing stability to the record carrier. By irradiating one or both separating layers a region of those separating layers is destroyed or altered whereby an opening is created and the reaction of the layers adjacent to the separating layer is no longer prevented in that region and a mark can be formed. Since either one or two reactions can take place if one or both separating layers are destroyed or altered multiple reflection levels for a mark can be obtained, thus enabling multilevel recording where a single mark can represent more information compared to the situation where only two reflection levels can be obtained. The size of the resulting opening determines the size of the mark and can thus be used to create a very small mark allowing high density recordings.
摘要翻译：记录载体包括三层，当被照射时彼此反应以在记录载体上形成标记。这三层由两个隔离层隔开，防止三层的直接接触，从而为记录载体提供稳定性。通过照射一个或两个分离层，这些分离层的区域被破坏或改变，由此产生开口，并且在该区域中不再防止与分离层相邻的层的反应，并且可以形成标记。由于如果一个或两个分离层被破坏或改变，则可以获得一个或两个反应的一个或两个反应，因此可以获得标记的多个反射水平，从而能够进行多级记录，其中单个标记可以表示更多的信息，与仅仅两个反射水平可以获得。所得到的开口的尺寸决定了标记的尺寸，因此可以用于产生允许高密度记录的非常小的标记。

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