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1. 发明申请

US20080316805A1 Electronic Circuit With a Memory Matrix 有权
标题翻译：具有存储矩阵的电子电路
公开(公告)号：US20080316805A1
公开(公告)日：2008-12-25
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储器单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是具有耦合到存储单元（16）的行的第一行导体（10）的控制电极的垂直晶体管，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在存储器单元所属的行对之间的节点（166）和第二行导体（12）之间。

2. 发明授权

US07679952B2 Electronic circuit with a memory matrix 有权
标题翻译：具有记忆矩阵的电子电路
公开(公告)号：US07679952B2
公开(公告)日：2010-03-16
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.
摘要翻译：在示例实施例中，电子电路包括具有存储器单元的行和列的存储器矩阵。为每行提供第一行导体。第二行导体对应于行对，每个连续的行与前面的行之一形成相应的对，使得每一对与下一对的一行重叠。为每个列提供列导体。每个存储单元包括存取晶体管，节点和第一和第二电阻存储器元件。存取晶体管具有耦合到存储单元行的第一行导体的控制电极，耦合在存储单元的列的列导体和节点之间的主电流通道。第一和第二电阻性存储器元件耦合在该存储器单元所属的行对之间的节点和第二行导体之间。

3. 发明申请

US20080258770A1 Single Threshold and Single Conductivity Type Logic 有权
标题翻译：单阈值和单电导型逻辑
公开(公告)号：US20080258770A1
公开(公告)日：2008-10-23
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主要的当前裸片耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

4. 发明授权

US07834668B2 Single threshold and single conductivity type amplifier/buffer 有权
标题翻译：单阈值和单导电型放大器/缓冲器
公开(公告)号：US07834668B2
公开(公告)日：2010-11-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03B1/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

5. 发明授权

US07671660B2 Single threshold and single conductivity type logic 有权
标题翻译：单阈值和单导电类型逻辑
公开(公告)号：US07671660B2
公开(公告)日：2010-03-02
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K17/16
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主电流路径耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

6. 发明申请

US20080252338A1 Single Threshold and Single Conductivity Type Amplifier/Buffer 有权
标题翻译：单阈值和单电导型放大器/缓冲器
公开(公告)号：US20080252338A1
公开(公告)日：2008-10-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K3/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

7. 发明申请

US20080279025A1 Electronic Circuit with Memory for Which a Threshold Level is Selected 审中-公开
标题翻译：具有选择阈值电平的具有存储器的电子电路
公开(公告)号：US20080279025A1
公开(公告)日：2008-11-13
申请号：US11568003
申请日：2005-04-21
申请人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
发明人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
IPC分类号： G11C7/02 , H03M7/00
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

8. 发明授权

US08081523B2 Circuit with a memory array and a reference level generator circuit 有权
标题翻译：具有存储器阵列和参考电平发生器电路的电路
公开(公告)号：US08081523B2
公开(公告)日：2011-12-20
申请号：US11813862
申请日：2006-01-05
申请人： Victor Martinus Van Acht , Nicolaas Lambert , Pierre Hermanus Woerlee
发明人： Victor Martinus Van Acht , Nicolaas Lambert , Pierre Hermanus Woerlee
IPC分类号： G11C5/14
CPC分类号： G11C7/14
摘要： A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.
摘要翻译：电路包括存储器单元阵列（10）。多个感测电路（20）耦合到相应存储单元（10）的输出（14），用于将存储单元（10）中的相应一个的输出信号与参考信号进行比较以形成数据信号来自存储单元（10）中的相应一个的输出信号。参考发生器电路（24,26）从一个和形成参考信号，其中寻址组的每个存储单元（10）中的每个相应的一个贡献作为存储单元的相应一个的输出信号的函数（10）。在超过参考信号的饱和距离上的输出信号值的贡献相等，并且在超过参考信号以下的饱和距离处的输出信号值的贡献相等。在单元格中存储多级数据的情况下，从基准电平以上和低于基准电平的中心电平到饱和电平的距离是相互不同的，其比率对应于已经被编程的单元计数的比率各级别。

9. 发明授权

US07643327B2 Driving a memory matrix of resistance hysteresis elements 有权
标题翻译：驱动电阻滞后元件的记忆矩阵
公开(公告)号：US07643327B2
公开(公告)日：2010-01-05
申请号：US11817715
申请日：2006-02-28
申请人： Teunis Jian Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jian Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C11/56
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。在所选行中的列端子和单元（20）的行端子之间施加电压差，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差被施加在所选列的单元（20）的列端子和行端子之间，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

10. 发明授权

US07580275B2 Control of a memory matrix with resistance hysteresis elements 有权
标题翻译：具有电阻滞后元件的存储矩阵的控制
公开(公告)号：US07580275B2
公开(公告)日：2009-08-25
申请号：US11817754
申请日：2006-03-03
申请人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
发明人： Teunis Jan Ikkink , Pierre Hermanus Woerlee , Victor Martinus Van Acht , Nicolaas Lambert , Albert W. Marsman
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

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