专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080279025A1 Electronic Circuit with Memory for Which a Threshold Level is Selected 审中-公开
标题翻译：具有选择阈值电平的具有存储器的电子电路
公开(公告)号：US20080279025A1
公开(公告)日：2008-11-13
申请号：US11568003
申请日：2005-04-21
申请人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
发明人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
IPC分类号： G11C7/02 , H03M7/00
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

2. 发明授权

US07679952B2 Electronic circuit with a memory matrix 有权
标题翻译：具有记忆矩阵的电子电路
公开(公告)号：US07679952B2
公开(公告)日：2010-03-16
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.
摘要翻译：在示例实施例中，电子电路包括具有存储器单元的行和列的存储器矩阵。为每行提供第一行导体。第二行导体对应于行对，每个连续的行与前面的行之一形成相应的对，使得每一对与下一对的一行重叠。为每个列提供列导体。每个存储单元包括存取晶体管，节点和第一和第二电阻存储器元件。存取晶体管具有耦合到存储单元行的第一行导体的控制电极，耦合在存储单元的列的列导体和节点之间的主电流通道。第一和第二电阻性存储器元件耦合在该存储器单元所属的行对之间的节点和第二行导体之间。

3. 发明申请

US20080258770A1 Single Threshold and Single Conductivity Type Logic 有权
标题翻译：单阈值和单电导型逻辑
公开(公告)号：US20080258770A1
公开(公告)日：2008-10-23
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主要的当前裸片耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

4. 发明申请

US20080316805A1 Electronic Circuit With a Memory Matrix 有权
标题翻译：具有存储矩阵的电子电路
公开(公告)号：US20080316805A1
公开(公告)日：2008-12-25
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储器单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是具有耦合到存储单元（16）的行的第一行导体（10）的控制电极的垂直晶体管，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在存储器单元所属的行对之间的节点（166）和第二行导体（12）之间。

5. 发明授权

US07834668B2 Single threshold and single conductivity type amplifier/buffer 有权
标题翻译：单阈值和单导电型放大器/缓冲器
公开(公告)号：US07834668B2
公开(公告)日：2010-11-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03B1/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

6. 发明授权

US07671660B2 Single threshold and single conductivity type logic 有权
标题翻译：单阈值和单导电类型逻辑
公开(公告)号：US07671660B2
公开(公告)日：2010-03-02
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K17/16
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主电流路径耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

7. 发明申请

US20080252338A1 Single Threshold and Single Conductivity Type Amplifier/Buffer 有权
标题翻译：单阈值和单电导型放大器/缓冲器
公开(公告)号：US20080252338A1
公开(公告)日：2008-10-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K3/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

8. 发明授权

US08823527B2 Consciousness monitoring 有权
标题翻译：意识监控
公开(公告)号：US08823527B2
公开(公告)日：2014-09-02
申请号：US13390520
申请日：2010-08-25
申请人： Sri Andari Husen , Bastiaan Feddes , Thomas Falck , Constant Paul Marie Jozef Baggen , Andre Melon Barroso , Mark Thomas Johnson , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
发明人： Sri Andari Husen , Bastiaan Feddes , Thomas Falck , Constant Paul Marie Jozef Baggen , Andre Melon Barroso , Mark Thomas Johnson , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
IPC分类号： G08B23/00
CPC分类号： A61B5/16 , A61B5/11 , G08B21/06
摘要： A method for automatically monitoring consciousness of a person and triggering an alarm if the monitored person is not in a state of full consciousness is provided. The method comprises the steps: monitoring at least one aspect of the behavior of the person (S1); analyzing whether the monitored behavior of the person corresponds to an expected behavior for a state of full consciousness or not (S2, S2′); triggering an alarm if the analysis results in that the detected behavior does not correspond to the expected behavior (S3).
摘要翻译：提供了一种自动监测人的意识并触发警报的方法，如果被监视者不处于全意识状态。该方法包括以下步骤：监视人的行为的至少一个方面（S1）; 分析人的监视行为是否对应于完全意识状态的预期行为（S2，S2'）; 如果分析导致检测到的行为不符合预期行为，则触发警报（S3）。

9. 发明申请

US20100234699A1 PROCESS AND SYSTEM FOR MONITORING EXERCISE MOTIONS OF A PERSON 有权
标题翻译：用于监测人员锻炼动作的过程和系统
公开(公告)号：US20100234699A1
公开(公告)日：2010-09-16
申请号：US12671733
申请日：2008-07-31
申请人： Gerd Lanfermann , Edwin Gerardus Johannes Maria Bongers , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
发明人： Gerd Lanfermann , Edwin Gerardus Johannes Maria Bongers , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
IPC分类号： A61B5/00
CPC分类号： A63B24/0006 , A63B2024/0009 , A63B2024/0012
摘要： The present invention relates to a process and a system for monitoring exercise motions of a person. The process comprises monitoring a first sensor signal from the person. While the first sensor signal does not deviate from a first sensor signal template by more than a pre-determined amount, signals from further sensors from the person are monitored, compared to templates processing and the comparison result is evaluated. If unit sensor signals deviate from the templates by more than a pre-determined value this is communicated to the person.
摘要翻译：本发明涉及一种用于监测人的运动运动的过程和系统。该过程包括监测来自人的第一传感器信号。虽然第一传感器信号没有偏离第一传感器信号模板超过预定量，但是与模板处理相比较，监视来自人的其他传感器的信号，并评估比较结果。如果单位传感器信号偏离模板超过预定值，则将其传达给人员。

10. 发明授权

US08818751B2 Interpreting angular orientation data 有权
标题翻译：解释角度定向数据
公开(公告)号：US08818751B2
公开(公告)日：2014-08-26
申请号：US13145662
申请日：2010-01-14
申请人： Victor Martinus Gerardus Van Acht , Edwin Gerardus Johannus Maria Bongers , Nicolaas Lambert
发明人： Victor Martinus Gerardus Van Acht , Edwin Gerardus Johannus Maria Bongers , Nicolaas Lambert
IPC分类号： G06F15/00 , G01B21/00 , A61B5/103 , A61B5/107
CPC分类号： A61B5/1038 , A61B5/1071 , A61B2562/0219
摘要： The invention relates to method and a system of interpreting angular orientation data. It is determined, whether the angular deviation of a current angular orientation (C) of a sensor device (12) from a last extreme angular orientation (L) currently decreases after having increased before up to a provisional new extreme angular orientation (P), thereby determining that the provisional new extreme angular orientation (P) is a new extreme angular orientation. Information relating to a new extreme angular orientation, such as an angular range of motion, may be output to a user.
摘要翻译：本发明涉及解释角度定向数据的方法和系统。确定传感器装置（12）的当前角度取向（C）与最后极端角度取向（L）的角度偏差在高达临时新的极限角度方向（P）之前是否增加之后目前减小，从而确定临时新的极角取向（P）是新的极端角度取向。关于新的极端角度取向（例如角度运动范围）的信息可以输出给用户。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式