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1. 发明授权

US09786692B2 Scan driving circuit and NAND logic operation circuit thereof 有权
公开(公告)号：US09786692B2
公开(公告)日：2017-10-10
申请号：US14433857
申请日：2015-01-28
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Chao Dai
IPC分类号： H01L27/12 , G02F1/1368 , H03K19/0944 , G09G3/36
CPC分类号： H01L27/124 , G02F1/1368 , G09G3/3677 , G09G2300/0408 , G09G2310/0291 , H01L27/1225 , H03K19/0944 , H03K19/09441 , H03K19/20
摘要： The invention provides a scan driving circuit for an oxide semiconductor thin film transistor and a NAND logic operation circuit thereof. The NAND logic operation circuit includes: a first inverter and a second inverter applied to a pull-down holding circuit of a GOA circuit, and multiple transistors. The invention uses the combination of NFTF and inverter to replace a function of original PMOS elements and thereby achieves characteristics similar to that of the original CMOS NAND operation circuit. Accordingly, the invention can solve the design problem of IGZO TFT single type of device logic operation circuit and thus is more suitable for integrating a large scale digital integrated circuit on a liquid crystal display device.

2. 发明申请

US20170229081A1 SCAN DRIVING CIRCUIT AND NAND LOGIC OPERATION CIRCUIT THEREOF 有权
公开(公告)号：US20170229081A1
公开(公告)日：2017-08-10
申请号：US14433857
申请日：2015-01-28
申请人： SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Chao DAI
IPC分类号： G09G3/36 , H03K19/0944 , H01L27/12 , G02F1/1368
CPC分类号： H01L27/124 , G02F1/1368 , G09G3/3677 , G09G2300/0408 , G09G2310/0291 , H01L27/1225 , H03K19/0944 , H03K19/09441 , H03K19/20
摘要： The invention provides a scan driving circuit for an oxide semiconductor thin film transistor and a NAND logic operation circuit thereof. The NAND logic operation circuit includes: a first inverter and a second inverter applied to a pull-down holding circuit of a GOA circuit, and multiple transistors. The invention uses the combination of NFTF and inverter to replace a function of original PMOS elements and thereby achieves characteristics similar to that of the original CMOS NAND operation circuit. Accordingly, the invention can solve the design problem of IGZO TFT single type of device logic operation circuit and thus is more suitable for integrating a large scale digital integrated circuit on a liquid crystal display device.

3. 发明申请

US20160112035A1 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
标题翻译：半导体器件，电子元件和电子器件
公开(公告)号：US20160112035A1
公开(公告)日：2016-04-21
申请号：US14882816
申请日：2015-10-14
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA
IPC分类号： H03K3/012 , H03K3/356 , H03K3/86 , H01L29/786 , H03K19/0944
CPC分类号： H03K3/012 , H01L27/1225 , H01L29/7869 , H03K3/037 , H03K3/356 , H03K3/86 , H03K5/134 , H03K19/09441 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H03K2005/00195
摘要： A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.
摘要翻译：半导体器件包括能够存储配置数据的逻辑电路。逻辑电路包括锁存电路，运算电路，延迟电路和第一输出定时产生电路。锁存电路具有接收脉冲信号和复位信号并输出第一信号的功能。延迟电路具有接收第一信号并输出第二信号的功能。第一个信号控制运算电路和延迟电路的电源。通过延迟第一信号以便对应于算术电路的关键路径中的延迟来获得第二信号。第一输出定时发生电路具有接收对第一信号和第二信号进行逻辑运算而获得的第三信号并输出复位信号的功能。

4. 发明申请

US20140104088A1 DIFFERENTIAL SWITCH DRIVE CIRCUIT AND CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：差分开关驱动电路和电流转向数字到模拟转换器
公开(公告)号：US20140104088A1
公开(公告)日：2014-04-17
申请号：US14133087
申请日：2013-12-18
申请人： PANASONIC CORPORATION
发明人： Toshinobu NAGASAWA , Michiko YAMADA , Heiji IKOMA
IPC分类号： H03M1/66 , H03K19/0185 , H03K3/013
CPC分类号： H03M1/66 , H03K3/013 , H03K17/162 , H03K19/0185 , H03K19/09432 , H03K19/09441 , H03K19/20
摘要： A differential switch drive circuit includes a current source, a current control circuit including a pair of transistors having a pair of differential input terminals, a pair of differential output terminals for outputting differential output voltages, and a common connection node connected to the current source, and load elements each connected to a corresponding one of the pair of differential output terminals. Currents flowing through the pair of transistors are controlled so that the sum of currents flowing through the load elements during a steady state of the differential output voltages is different from the sum of currents flowing through the load elements during a transient state of the differential output voltages.
摘要翻译：差分开关驱动电路包括电流源，电流控制电路，包括具有一对差分输入端子的一对晶体管，用于输出差分输出电压的一对差分输出端子和连接到电流源的公共连接节点，以及各自连接到所述一对差分输出端子中的对应的一个的负载元件。控制流过该对晶体管的电流，使得在差分输出电压的稳定状态期间流过负载元件的电流的总和不同于在差分输出电压的瞬态期间流过负载元件的电流之和。

5. 发明申请

US20100253393A1 BUFFER AND DISPLAY DEVICE 有权
标题翻译：缓冲和显示设备
公开(公告)号：US20100253393A1
公开(公告)日：2010-10-07
申请号：US12734691
申请日：2008-08-19
申请人： Etsuo Yamamoto , Yuhichiro Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
发明人： Etsuo Yamamoto , Yuhichiro Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
IPC分类号： H03K3/00
CPC分类号： G09G3/3677 , G09G2310/0291 , G09G2330/021 , H03K19/0013 , H03K19/01714 , H03K19/018507 , H03K19/09441
摘要： A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.
摘要翻译：包括晶体管的单相输入，所述晶体管仅具有单一类型的沟道极性，该缓冲器包括：缓冲器部分32，包括由串联连接的两个n沟道晶体管构成的第一串联电路，第二系列由在连接点OUT处彼此串联连接的两个n沟道晶体管形成的电路，以及电容器; 以及反相信号生成部，用于从输入信号产生反相信号，所述反相信号生成部包括n沟道晶体管，但不包括p沟道晶体管，所述输入信号被输入到所述晶体管的各个栅极，所述反相信号生成部信号被输入到晶体管4的栅极，并且输出信号经由连接点OUT输出。使用缓冲器，可以减少消耗电流并且增加用于负载的电流驱动。

6. 发明申请

US20080036712A1 Logic gate, scan driver and organic light emitting diode display using the same 有权
标题翻译：逻辑门，扫描驱动器和有机发光二极管显示使用相同
公开(公告)号：US20080036712A1
公开(公告)日：2008-02-14
申请号：US11826315
申请日：2007-07-13
申请人： Bo Yong Chung
发明人： Bo Yong Chung
IPC分类号： G09G3/32 , H03K19/084 , H03K19/20
CPC分类号： H03K19/09441 , G09G3/3266 , G09G2300/0417 , G11C19/00
摘要： An organic light emitting diode display, including pixel circuits coupled to respective data lines and scan lines, a data driver configured to supply data signals to the data lines, and a scan driver configured to provide scan signals to the scan lines, wherein the scan driver includes at least one decoder including a plurality of NOR gates, the decoder configured to provide a first plurality of signals, and a plurality of NAND gates coupled to respective scan lines, the NAND gates being configured to perform a NAND operation on the first plurality of signals and to provide scan signals to the scan lines, wherein all transistors in each of the NOR gates and each of the NAND gates are a same type of MOS transistor.
摘要翻译：一种有机发光二极管显示器，包括耦合到相应数据线和扫描线的像素电路，配置成向数据线提供数据信号的数据驱动器，以及配置成向扫描线提供扫描信号的扫描驱动器，其中扫描驱动器包括至少一个包括多个NOR门的解码器，所述解码器被配置为提供第一多个信号，以及耦合到相应扫描线的多个NAND门，所述NAND门被配置为对所述第一多个信号执行NAND运算信号并向扫描线提供扫描信号，其中每个NOR门和每个NAND门中的所有晶体管都是相同类型的MOS晶体管。

7. 发明授权

US06407434B1 Hexagonal architecture 失效
标题翻译：六角架构
公开(公告)号：US06407434B1
公开(公告)日：2002-06-18
申请号：US08517142
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L2144
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H01L29/0657 , H01L2924/0002 , H03K19/09441 , H03K19/0948 , H01L2924/00
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

8. 发明授权

US6097073A Triangular semiconductor or gate 失效
标题翻译：三角半导体或门
公开(公告)号：US6097073A
公开(公告)日：2000-08-01
申请号：US517892
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/772
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

9. 发明授权

US5903170A Digital logic design using negative differential resistance diodes and field-effect transistors 失效
标题翻译：使用负差分电阻二极管和场效应晶体管的数字逻辑设计
公开(公告)号：US5903170A
公开(公告)日：1999-05-11
申请号：US868270
申请日：1997-06-03
申请人： Shriram Kulkarni , Pinaki Mazumder , George I. Haddad
发明人： Shriram Kulkarni , Pinaki Mazumder , George I. Haddad
IPC分类号： H03K19/0944 , H03K19/10
CPC分类号： B82Y10/00 , H03K19/09441 , H03K19/10
摘要： A digital logic gate circuit including a logic block, clock transistor, bias transistor and a negative differential resistance (NDR) diode which acts as an active load for the circuit. The logic block, comprising a plurality of field effect transistors whose control terminals receive the set of input signals to the logic gate, determines the gate function such as inversion, NAND, NOR, MAJORITY, etc. The clock transistor is connected in series with the logic block and the bias transistor is connected in parallel across this series combination. The terminal of the NDR diode affixed to the common terminal of the bias transistor and the logic block forms the output for the logic circuit. NDR diodes include but are not limited to devices such as tunnel diodes and resonant tunneling diodes (RTDs). The folded I-V characteristic of an NDR diode allows the circuits to operate in a bistable clocked mode, where the circuit output latches its state and changes only when the clock signal is active. The circuit topology allows logic functions to be implemented in a compact manner, thus reducing the propagation delay for the signals, and reducing the overall complexity and delay of arbitrary logic circuits. Thus, performance improvements result from the compactness of logic design as well as the elimination of a pipeline latch area and delay overheads.
摘要翻译：数字逻辑门电路包括逻辑块，时钟晶体管，偏置晶体管和用作电路的有源负载的负差分电阻（NDR）二极管。该逻辑块包括多个场效应晶体管，其控制端接收到逻辑门的输入信号，确定诸如反相，NAND，NOR，NOR，MAJORITY等门功能。时钟晶体管与逻辑块和偏置晶体管并联连接在该串联组合上。固定在偏置晶体管的公共端子上的NDR二极管的端子和逻辑块形成逻辑电路的输出。 NDR二极管包括但不限于诸如隧道二极管和谐振隧道二极管（RTD）的器件。 NDR二极管的折叠I-V特性允许电路以双稳态时钟模式工作，其中电路输出锁存其状态，只有在时钟信号有效时才会改变。电路拓扑允许以紧凑的方式实现逻辑功能，从而减少信号的传播延迟，并降低任意逻辑电路的整体复杂度和延迟。因此，性能改进是由于逻辑设计的紧凑性以及消除流水线锁存区域和延迟开销造成的。

10. 发明授权

US5834821A Triangular semiconductor "AND" gate device 失效
标题翻译：三角半导体“AND”门装置
公开(公告)号：US5834821A
公开(公告)日：1998-11-10
申请号：US517479
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L27/088 , H01L29/78
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

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