专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180287611A1 LOW POWER LOGIC FAMILY 审中-公开
公开(公告)号：US20180287611A1
公开(公告)日：2018-10-04
申请号：US15768549
申请日：2016-10-24
申请人： Ari PAASIO
发明人： Ari PAASIO
IPC分类号： H03K19/00 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/0013 , G05F3/20 , H03K19/0027 , H03K19/01707 , H03K19/09441
摘要： According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output, This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs. The logic type offers higher operation speed compared to the existing solutions.

2. 发明授权

US09438207B2 Semiconductor device, electronic component, and electronic device 有权
标题翻译：半导体装置，电子部件和电子装置
公开(公告)号：US09438207B2
公开(公告)日：2016-09-06
申请号：US14882816
申请日：2015-10-14
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki Kurokawa
IPC分类号： G06F7/38 , H03K19/173 , H03K3/012 , H01L29/786 , H03K19/0944 , H03K3/86 , H03K3/356
CPC分类号： H03K3/012 , H01L27/1225 , H01L29/7869 , H03K3/037 , H03K3/356 , H03K3/86 , H03K5/134 , H03K19/09441 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H03K2005/00195
摘要： A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.
摘要翻译：半导体器件包括能够存储配置数据的逻辑电路。逻辑电路包括锁存电路，运算电路，延迟电路和第一输出定时产生电路。锁存电路具有接收脉冲信号和复位信号并输出第一信号的功能。延迟电路具有接收第一信号并输出第二信号的功能。第一个信号控制运算电路和延迟电路的电源。通过延迟第一信号以便对应于算术电路的关键路径中的延迟来获得第二信号。第一输出定时发生电路具有接收对第一信号和第二信号进行逻辑运算而获得的第三信号并输出复位信号的功能。

3. 发明授权

US09214475B2 All N-type transistor inverter circuit 有权
标题翻译：所有N型晶体管逆变电路
公开(公告)号：US09214475B2
公开(公告)日：2015-12-15
申请号：US13937752
申请日：2013-07-09
申请人： Pixtronix, Inc.
发明人： Ilias Pappas
IPC分类号： G09G3/20 , H01L27/12 , G09G3/34 , G11C19/28 , H03K19/0944 , H03K19/017 , H03K19/20
CPC分类号： H01L27/1225 , G09G3/3433 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291 , G09G2330/021 , G11C19/28 , H01L27/1255 , H03K19/01714 , H03K19/09441 , H03K19/20
摘要： This disclosure provides systems, methods and apparatus for an all n-type transistor inverter circuit. A circuit can include an input thin film transistor (TFT), a pull-down TFT, a discharge TFT, a first pull-up TFT, a second pull-up TFT, and a floating capacitor. The circuit also can include first and second low-voltage voltage sources and first and second high-voltage voltage sources. The TFTs, the capacitor, and the voltage sources can be coupled such that an output of the circuit is the logical opposite of an input of the circuit. In some implementations, the circuit can exhibit zero DC current in both logic states and can output voltages substantially equal to the voltage output by the first low-voltage voltage source and the second high-voltage voltage source. In some implementations, the circuit can be used to construct D flip-flops, buffers, and controllers for an active matrix electronic display.
摘要翻译：本公开提供了用于全n型晶体管反相器电路的系统，方法和装置。电路可以包括输入薄膜晶体管（TFT），下拉式TFT，放电TFT，第一上拉TFT，第二上拉TFT和浮动电容器。电路还可以包括第一和第二低压电压源以及第一和第二高压电压源。 TFT，电容器和电压源可以被耦合，使得电路的输出与电路的输入逻辑相反。在一些实施方案中，电路可以在两个逻辑状态下呈现零直流电流，并且可以输出基本上等于由第一低压电压源和第二高压电压源输出的电压的电压。在一些实现中，该电路可用于构建用于有源矩阵电子显示器的D触发器，缓冲器和控制器。

4. 发明申请

US20140225641A1 PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：可编程逻辑器件和半导体器件
公开(公告)号：US20140225641A1
公开(公告)日：2014-08-14
申请号：US14170825
申请日：2014-02-03
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Munehiro Kozuma , Yoshiyuki Kurokawa , Takayuki Ikeda , Takeshi Aoki
IPC分类号： H03K19/177
CPC分类号： H03K19/0013 , H01L27/1225 , H01L27/124 , H01L29/24 , H01L29/7869 , H03K19/09441 , H03K19/1737 , H03K19/17728 , H03K19/17748 , H03K19/1776
摘要： A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.
摘要翻译：可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据来控制。每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。

5. 发明授权

US08508460B2 Scanning signal line drive circuit and display device including the same 有权
标题翻译：扫描信号线驱动电路和显示装置包括相同
公开(公告)号：US08508460B2
公开(公告)日：2013-08-13
申请号：US13512892
申请日：2010-10-14
申请人： Yoshihisa Takahashi , Yasuaki Iwase
发明人： Yoshihisa Takahashi , Yasuaki Iwase
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G11C19/28 , H03K19/01728 , H03K19/09441
摘要： It is an object to realize a gate driver that can cause a scanning signal to quickly fall after a charge period in each row ends.A gate driver is configured by two shift registers. In an n-th stage bistable circuit (SR(n)) in an entire shift register (410), a region netA connected to a gate terminal of a thin-film transistor that increases a potential of an output node for outputting a state signal (Q) based on a first clock (CKA) is set to an on level based on the state signal (Q) outputted from an (n−2)-th stage bistable circuit (SR(n−2), the region netA is set to an off level based on the state signal (Q) outputted from an (n+2)-th stage bistable circuit (SR(n+2)), and the output node is set to an off level based on the state signal (Q) outputted from an (n+3)-th stage bistable circuit (SR(n+3)).
摘要翻译：其目的是实现一个栅极驱动器，其可以在每行的充电周期结束后使扫描信号快速下降。门驱动器由两个移位寄存器配置。在整个移位寄存器（410）中的第n级双稳态电路（SR（n））中，连接到薄膜晶体管的栅极端子的区域netA，其增加用于输出状态信号的输出节点的电位基于从第（n-2）级双稳态电路（SR（n-2））输出的状态信号（Q），基于第一时钟（CKA）的区域netA为基于从第（n + 2）级双稳态电路（SR（n + 2））输出的状态信号（Q）设置为关闭电平，并且基于状态信号将输出节点设置为关闭电平（n + 3）级双稳态电路（SR（n + 3））输出的输出信号（Q）。

6. 发明申请

US20130049806A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130049806A1
公开(公告)日：2013-02-28
申请号：US13572951
申请日：2012-08-13
申请人： Jun Koyama
发明人： Jun Koyama
IPC分类号： H03K19/0944
CPC分类号： H03K19/09441 , H03K19/01714
摘要： A semiconductor device is provided, which includes a switch having a first transistor and a logic circuit having an output terminal. The logic circuit includes a bootstrap circuit having at least one second transistor. The bootstrap circuit is electrically connected to the output terminal. The first transistor and the second transistor have the same conductivity type. Each of the first transistor and the second transistor includes an oxide semiconductor layer including a channel formation region and a pair of gate electrodes with the oxide semiconductor layer provided therebetween.
摘要翻译：提供一种半导体器件，其包括具有第一晶体管和具有输出端子的逻辑电路的开关。逻辑电路包括具有至少一个第二晶体管的自举电路。引导电路电连接到输出端子。第一晶体管和第二晶体管具有相同的导电类型。第一晶体管和第二晶体管中的每一个包括包括沟道形成区域的氧化物半导体层和设置在其间的氧化物半导体层的一对栅电极。

7. 发明授权

US08354979B2 Logic gate, scan driver and organic light emitting diode display using the same 有权
标题翻译：逻辑门，扫描驱动器和有机发光二极管显示使用相同
公开(公告)号：US08354979B2
公开(公告)日：2013-01-15
申请号：US11826315
申请日：2007-07-13
申请人： Bo Yong Chung
发明人： Bo Yong Chung
IPC分类号： G09G3/32
CPC分类号： H03K19/09441 , G09G3/3266 , G09G2300/0417 , G11C19/00
摘要： An organic light emitting diode display, including pixel circuits coupled to respective data lines and scan lines, a data driver configured to supply data signals to the data lines, and a scan driver configured to provide scan signals to the scan lines, wherein the scan driver includes at least one decoder including a plurality of NOR gates, the decoder configured to provide a first plurality of signals, and a plurality of NAND gates coupled to respective scan lines, the NAND gates being configured to perform a NAND operation on the first plurality of signals and to provide scan signals to the scan lines, wherein all transistors in each of the NOR gates and each of the NAND gates are a same type of MOS transistor.
摘要翻译：一种有机发光二极管显示器，包括耦合到相应数据线和扫描线的像素电路，配置成向数据线提供数据信号的数据驱动器，以及配置成向扫描线提供扫描信号的扫描驱动器，其中扫描驱动器包括至少一个包括多个NOR门的解码器，所述解码器被配置为提供第一多个信号，以及耦合到相应扫描线的多个NAND门，所述NAND门被配置为对所述第一多个信号执行NAND运算信号并向扫描线提供扫描信号，其中每个NOR门和每个NAND门中的所有晶体管都是相同类型的MOS晶体管。

8. 发明申请

US20100194430A1 RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS 有权
标题翻译：可重构逻辑单元制造双栅MOSFET晶体管
公开(公告)号：US20100194430A1
公开(公告)日：2010-08-05
申请号：US12668135
申请日：2008-07-11
申请人： Ian D. O'Connor , Ilham Hassoune
发明人： Ian D. O'Connor , Ilham Hassoune
IPC分类号： H03K19/0944
CPC分类号： H03K19/09441 , H03K19/0813 , H03K19/1738
摘要： Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be processed. The cell contains, between the ground and the output (F) of the cell, at least one first branch including n dual gate N-type MOSFET transistors (M1,M2) in series and n−1 branches in parallel with the first branch, each provided with a dual gate N-type MOSFET transistor (M3), each of the logic functions corresponding to a given configuration of the cell. A specific set of control signals (C1,C2) is applied on the rear gates of at least one portion of the transistors (M2,M3), each control signal (C1,C2) being capable of setting the transistor (M2,M3) to a particular operating mode.
摘要翻译：基于包括n个输入（A，B），n大于或等于2的双栅极MOSFET晶体管（DG MOSFET）的可重构逻辑单元，并且能够执行至少四个逻辑功能，在n个输入（A ，B）可以被处理。该单元在单元的接地和输出（F）之间包含至少一个第一分支，其包括串联的n个双栅极N型MOSFET晶体管（M1，M2）和与第一分支并联的n-1个分支，每个具有双栅极N型MOSFET晶体管（M3），每个逻辑功能对应于单元的给定配置。在晶体管（M2，M3）的至少一部分的后栅极上施加特定的一组控制信号（C1，C2），每个控制信号（C1，C2）能够设置晶体管（M2，M3）到特定的操作模式。

9. 发明申请

US20090028200A1 LASER DIODE DRIVE CIRCUIT, ELECTRONIC CIRCUIT, METHOD FOR CONTROLLING LASER DIODE DRIVE CIRCUIT, AND METHOD FOR CONTROLLING DUTY 失效
标题翻译：激光二极管驱动电路，电子电路，用于控制激光二极管驱动电路的方法及其控制方法
公开(公告)号：US20090028200A1
公开(公告)日：2009-01-29
申请号：US12241927
申请日：2008-09-30
申请人： Hidetoshi NAITO
发明人： Hidetoshi NAITO
IPC分类号： H01S3/00
CPC分类号： H01S5/06213 , H01S5/0427 , H01S5/06825 , H03K5/1565 , H03K19/018514 , H03K19/09441
摘要： A laser diode drive circuit includes: a duty control amplifier (23) that controls the duty ratio of a main signal for laser control in accordance with a duty control signal; and an AND gate (22) that outputs the duty control signal to the duty control amplifier (23), and outputs a duty control signal that controls the duty ratio of the main signal to be 0% in the duty control amplifier in accordance with a shutdown signal of a laser diode. With this structure, there is no need to input the main signal having the duty ratio controlled to a logic circuit that becomes unstable. Thus, outputs from a semiconductor laser can be shut down, and the output duty can be controlled in a stable manner.
摘要翻译：激光二极管驱动电路包括：占空比控制放大器（23），其根据占空比控制信号控制用于激光控制的主信号的占空比; 以及将占空比控制信号输出到占空比控制放大器（23）的与门（22），并且根据占空比控制放大器（23）输出占空比控制信号，该占空比控制信号在占空比控制放大器中控制主信号的占空比为0％激光二极管的关断信号。利用这种结构，不需要将占空比的主信号输入到不稳定的逻辑电路。因此，可以关闭来自半导体激光器的输出，并且可以稳定地控制输出占空比。

10. 发明申请

US20080315918A1 Thin film transistor logic 失效
标题翻译：薄膜晶体管逻辑
公开(公告)号：US20080315918A1
公开(公告)日：2008-12-25
申请号：US11821068
申请日：2007-06-20
申请人： Hao Luo , Ping Mei , Carl P. Tausig
发明人： Hao Luo , Ping Mei , Carl P. Tausig
IPC分类号： H03K19/0175
CPC分类号： H03K19/09441
摘要： A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays.
摘要翻译：可以完全由相同导电类型的TFT制造的薄膜逻辑电路包括连接到电源电压的逻辑级和连接到由电源电压和接地提供的较宽电压范围的电平转换器。逻辑电路产生具有从地到电源电压的完整轨到轨信号范围的输出信号，并且可以实现或包括诸如逆变器，NAND门或NOR门的基本逻辑组件或更复杂的电路，其中许多基本逻辑元件级联在一起。这样的逻辑电路可以直接在柔性结构或大面积上制造，例如在平板显示器中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式