专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100299494A1 MEMORY WITH BLOCK-ERASABLE LOCATIONS AND A LINKED CHAIN OF POINTERS TO LOCATE BLOCKS WITH POINTER INFORMATION 审中-公开
标题翻译：具有可擦除位置的记忆体和连接的指示器链以定位具有指针信息的块
公开(公告)号：US20100299494A1
公开(公告)日：2010-11-25
申请号：US12158993
申请日：2006-12-13
申请人： Victor M.G. Van Acht , Nicolaas Lambert
发明人： Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： A memory apparatus has a main memory (10) that comprises a plurality of physical blocks of memory locations. The main memory (10), for example a flash memory, supports erasing of at least a physical block at a time. A chain of pointers (72, 75) that ultimately points to pointing information such as a logical address to physical address mapping table is stored in the main memory (10), each pointer (72, 75) being stored in a respective one of the blocks (70, 74), each non-final pointer (72) in the chain pointing to a respective block (74) that contains a next pointer in the chain. On start up of main memory (10) the pointing information is located by following said chain, using the pointers from the main memory. In normal operation direct pointers stored in a RAM are preferably used.
摘要翻译：存储装置具有主存储器（10），其包括多个存储器位置的物理块。主存储器（10），例如闪速存储器，一次支持擦除至少一个物理块。最终指向诸如逻辑地址到物理地址映射表的指向信息的指针链（72,75）被存储在主存储器（10）中，每个指针（72,75）存储在主存储器块（70,74）中，链中的每个非最终指针（72）指向包含链中的下一个指针的相应块（74）。在主存储器（10）的启动时，使用来自主存储器的指针，通过跟随所述链来定位指向信息。在正常操作中，优选地使用存储在RAM中的直接指针。

2. 发明申请

US20090070637A1 ELECTRONIC CIRCUIT WITH A MEMORY MATRIX THAT STORES PAGES INCLUDING EXTRA DATA 有权
标题翻译：具有包含额外数据的存储器的存储器矩阵的电子电路
公开(公告)号：US20090070637A1
公开(公告)日：2009-03-12
申请号：US12281983
申请日：2007-03-05
申请人： Victor M.G. Van Acht , Nicolaas Lambert
发明人： Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： G06F11/08
CPC分类号： G06F11/1068
摘要： An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24). The processing circuit (12) performs further processing using the data from the extra data (22) or the corrected extra data, dependent on whether the error detection indicates an error in the extra data (22).
摘要翻译：一种装置包括具有带有存储单元的行和列的矩阵（10）的存储器。读取访问电路（14,16,18）执行读取命令以从矩阵（10）读取包括来自存储器单元的行的数据的检索单元，并从检索单元输出数据。耦合到读取访问电路（14,16,18）的处理电路（12）被配置为执行涉及发出读取命令的额外读取操作，接收附加数据（24），仅对附加数据执行错误检测 24），使用其中对所述额外数据进行编码的错误检测码，根据来自所述有效载荷数据（22）的检索单元的数据，使用来自所述附加数据（24）的数据对所述数据进行有条件地执行错误校正，所述纠错码其中检索单元被编码，如果错误检测指示额外数据（24）中的错误。处理电路（12）根据来自额外数据（22）的数据或校正的附加数据，根据该错误检测是否指示额外数据（22）中的错误，进行进一步处理。

3. 发明申请

US20090072212A1 ANTI-FUSE MEMORY DEVICE 有权
标题翻译：防静电存储器件
公开(公告)号：US20090072212A1
公开(公告)日：2009-03-19
申请号：US11914662
申请日：2006-05-04
申请人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M.G. Van Acht , Nicolaas Lambert
发明人： Paul Van Der Sluis , Andrei Mijiritskii , Pierre H. Woerlee , Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.
摘要翻译：一次性可编程（OTP）存储器单元（10），包括涂覆有第二导电稳定过渡化合物（14）的第一金属层（12），其间具有绝缘层（16）。第一层和第二层（12,14）根据它们之间的吉布斯自由能的差异来选择，这决定了由于两种材料之间的放热化学反应而产生的化学能。第一层和第二层（12,14）的材料本身是高度热稳定的，但是当向单元（10）施加电压时，导致绝缘层（16）的局部击穿产生热点（18 ），其在第一和第二层（12,14）之间引起放热化学反应。放热反应产生足够的热量（20）以在电池上产生短路并因此降低其电阻。

4. 发明申请

US20080270681A1 Non-Volatile Memory with Block Erasable Locations 有权
标题翻译：具有块可擦除位置的非易失性存储器
公开(公告)号：US20080270681A1
公开(公告)日：2008-10-30
申请号：US12158978
申请日：2006-12-13
申请人： Victor M.G. Van Acht , Nicolaas Lambert
发明人： Victor M.G. Van Acht , Nicolaas Lambert
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： A main memory (10) comprises a plurality of physical blocks of memory locations. The main memory (10) supports erasing of at least a physical block at a time. Pointer information is stored in a subset (40, 42) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block (40) in the subset (40, 42). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block (42) of the subset (40, 42) at least after the first block (40) has been filled. The first block (40) is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset (40, 42) contains a most recent version of the pointing information.
摘要翻译：主存储器（10）包括存储器位置的多个物理块。主存储器（10）一次支持擦除至少一个物理块。指针信息被存储在块的子集（40,42）中，用于标识被分配给各个功能的各个物理块。指向信息的连续版本存储在最初在子集（40,42）中的第一块（40）中的彼此不同的存储器位置处。至少在第一块（40）已被填充之后，比连续版本更新的指向信息的后续版本被存储在子集（40,42）的第二块（42）中。第一块（40）在存储后续版本之后被擦除。在主存储器的启动时，通过测试子集（40,42）中的哪个块包含指向信息的最新版本来恢复指向信息。

5. 发明授权

US08823527B2 Consciousness monitoring 有权
标题翻译：意识监控
公开(公告)号：US08823527B2
公开(公告)日：2014-09-02
申请号：US13390520
申请日：2010-08-25
申请人： Sri Andari Husen , Bastiaan Feddes , Thomas Falck , Constant Paul Marie Jozef Baggen , Andre Melon Barroso , Mark Thomas Johnson , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
发明人： Sri Andari Husen , Bastiaan Feddes , Thomas Falck , Constant Paul Marie Jozef Baggen , Andre Melon Barroso , Mark Thomas Johnson , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
IPC分类号： G08B23/00
CPC分类号： A61B5/16 , A61B5/11 , G08B21/06
摘要： A method for automatically monitoring consciousness of a person and triggering an alarm if the monitored person is not in a state of full consciousness is provided. The method comprises the steps: monitoring at least one aspect of the behavior of the person (S1); analyzing whether the monitored behavior of the person corresponds to an expected behavior for a state of full consciousness or not (S2, S2′); triggering an alarm if the analysis results in that the detected behavior does not correspond to the expected behavior (S3).
摘要翻译：提供了一种自动监测人的意识并触发警报的方法，如果被监视者不处于全意识状态。该方法包括以下步骤：监视人的行为的至少一个方面（S1）; 分析人的监视行为是否对应于完全意识状态的预期行为（S2，S2'）; 如果分析导致检测到的行为不符合预期行为，则触发警报（S3）。

6. 发明授权

US08081523B2 Circuit with a memory array and a reference level generator circuit 有权
标题翻译：具有存储器阵列和参考电平发生器电路的电路
公开(公告)号：US08081523B2
公开(公告)日：2011-12-20
申请号：US11813862
申请日：2006-01-05
申请人： Victor Martinus Van Acht , Nicolaas Lambert , Pierre Hermanus Woerlee
发明人： Victor Martinus Van Acht , Nicolaas Lambert , Pierre Hermanus Woerlee
IPC分类号： G11C5/14
CPC分类号： G11C7/14
摘要： A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.
摘要翻译：电路包括存储器单元阵列（10）。多个感测电路（20）耦合到相应存储单元（10）的输出（14），用于将存储单元（10）中的相应一个的输出信号与参考信号进行比较以形成数据信号来自存储单元（10）中的相应一个的输出信号。参考发生器电路（24,26）从一个和形成参考信号，其中寻址组的每个存储单元（10）中的每个相应的一个贡献作为存储单元的相应一个的输出信号的函数（10）。在超过参考信号的饱和距离上的输出信号值的贡献相等，并且在超过参考信号以下的饱和距离处的输出信号值的贡献相等。在单元格中存储多级数据的情况下，从基准电平以上和低于基准电平的中心电平到饱和电平的距离是相互不同的，其比率对应于已经被编程的单元计数的比率各级别。

7. 发明授权

US07889630B2 Record carrier 失效
标题翻译：记录载体
公开(公告)号：US07889630B2
公开(公告)日：2011-02-15
申请号：US10533730
申请日：2003-10-14
申请人： Nicolaas Lambert , Adrianus Johannes Maria Denissen
发明人： Nicolaas Lambert , Adrianus Johannes Maria Denissen
IPC分类号： G11B7/24
CPC分类号： G11B7/00736 , G11B7/24094 , G11B20/00086 , G11B20/00876 , G11B20/1883 , G11B20/1889 , G11B23/40 , G11B27/32 , G11B2220/20
摘要： The invention relates to a record carrier (1) comprising an area for storing data, the record carrier adhering to a pre-defined, standardized condition with respect to a physical parameter. The record carrier comprises parameter information on the physical parameter, which parameter information is of a higher precision than the precision of the physical parameter mentioned in the pre-defined, standardized condition. Using this high precision parameter information, it is possible to derive the exact position of a visible image pixel data making up a label. This parameter information thus enables a recorder to write a visible label on the record carrier according to the invention.
摘要翻译：本发明涉及一种记录载体（1），其包括用于存储数据的区域，所述记录载体相对于物理参数粘附到预定义的标准化状态。记录载体包括物理参数的参数信息，该参数信息的精度高于预定义的标准化条件中提到的物理参数的精度。使用这种高精度参数信息，可以导出构成标签的可见图像像素数据的确切位置。因此，该参数信息使得记录器能够在根据本发明的记录载体上写入可见标签。

8. 发明授权

US07831790B2 Universal memory device having a profile storage unit 有权
标题翻译：具有简档存储单元的通用存储器件
公开(公告)号：US07831790B2
公开(公告)日：2010-11-09
申请号：US10549367
申请日：2004-03-17
申请人： Nicolaas Lambert , Adrianus Johannes Maria Denissen , Wilhelmus Franciscus Johannes Fontijn , Robert Jochemsen
发明人： Nicolaas Lambert , Adrianus Johannes Maria Denissen , Wilhelmus Franciscus Johannes Fontijn , Robert Jochemsen
IPC分类号： G06F13/10
CPC分类号： G06F21/78 , G06F21/79 , G06F2221/2141 , G11C7/1045 , G11C7/24 , G11C16/22
摘要： A universal memory device is presented that provides adaptability to existing hardware and software environments. The memory can “mimic” existing memory technology combining the advantages of integrating all memory capacity into one single technology and still providing the implicit protections and access characteristics known from the different existing memory technologies. The memory device comprises a memory having low-latency, rewritable, non-volatile memory cells, a profile storage unit connected with the memory and comprising access information allocated to a set of request information elements (request profile), such that the access information indicates whether an access request to said memory, the access request having the request profile, is to be allowed or rejected, and an access control unit communicating with the profile storage unit and the memory, and adapted to allow or reject an incoming access request in dependence on the access information allocated to the request profile of the access request.
摘要翻译：提出了一种提供对现有硬件和软件环境的适应性的通用存储器件。存储器可以“模拟”现有存储器技术，结合将所有存储器容量集成到一个单一技术中并且仍然提供从不同现有存储器技术已知的隐式保护和访问特性的优点。存储装置包括具有低等待时间，可重写，非易失性存储器单元的存储器，与存储器连接的简档存储单元，并且包括分配给一组请求信息元素（请求简档）的访问信息，使得访问信息指示是否允许或拒绝对所述存储器的访问请求，具有请求简档的访问请求，以及与简档存储单元和存储器通信的访问控制单元，并且适于依赖于允许或拒绝传入的访问请求关于分配给访问请求的请求简档的访问信息。

9. 发明申请

US20100234699A1 PROCESS AND SYSTEM FOR MONITORING EXERCISE MOTIONS OF A PERSON 有权
标题翻译：用于监测人员锻炼动作的过程和系统
公开(公告)号：US20100234699A1
公开(公告)日：2010-09-16
申请号：US12671733
申请日：2008-07-31
申请人： Gerd Lanfermann , Edwin Gerardus Johannes Maria Bongers , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
发明人： Gerd Lanfermann , Edwin Gerardus Johannes Maria Bongers , Nicolaas Lambert , Victor Martinus Gerardus Van Acht
IPC分类号： A61B5/00
CPC分类号： A63B24/0006 , A63B2024/0009 , A63B2024/0012
摘要： The present invention relates to a process and a system for monitoring exercise motions of a person. The process comprises monitoring a first sensor signal from the person. While the first sensor signal does not deviate from a first sensor signal template by more than a pre-determined amount, signals from further sensors from the person are monitored, compared to templates processing and the comparison result is evaluated. If unit sensor signals deviate from the templates by more than a pre-determined value this is communicated to the person.
摘要翻译：本发明涉及一种用于监测人的运动运动的过程和系统。该过程包括监测来自人的第一传感器信号。虽然第一传感器信号没有偏离第一传感器信号模板超过预定量，但是与模板处理相比较，监视来自人的其他传感器的信号，并评估比较结果。如果单位传感器信号偏离模板超过预定值，则将其传达给人员。

10. 发明申请

US20100232245A1 ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION 有权
标题翻译：包含记忆矩阵的电子电路和用于BITLINE噪声补偿的读取方法
公开(公告)号：US20100232245A1
公开(公告)日：2010-09-16
申请号：US12293817
申请日：2007-03-27
申请人： Victor M. G. Van Acht , Nicolaas Lambert
发明人： Victor M. G. Van Acht , Nicolaas Lambert
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C7/062 , G11C7/14 , G11C7/18
摘要： Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).
摘要翻译：从具有多个位线（12）的存储矩阵（10）中读取数据。差分读出放大器（14）在第一输入端接收从位线（12）中的第一位导出的信号。差分读出放大器（14）从参考电路（15）的参考输出接收参考信号到第二输入端。与位线（12）中的第一位相邻的位线（12）中的第二位被耦合到参考电路（15），使得位的第二位上的位线信号值行（12）影响参考输出上的参考信号值，至少部分地再现位线信号值（12）上的位线信号值（12）对第二位线（12）上的串扰的影响第一个位线（12）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式