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    • 4. 发明授权
    • 파워 트랜지스터가 내장된 집적회로 및 그 제조 방법
    • 集成电路复用功率晶体管及其制造方法
    • KR100777161B1
    • 2007-11-16
    • KR1020060055871
    • 2006-06-21
    • 주식회사 케이이씨
    • 김동수김원찬김인수서송하정영태
    • H01L29/78H01L29/80H01L21/337H01L21/20
    • H01L27/082H01L21/8222
    • An integrated circuit having a power transistor and a manufacturing method thereof are provided to increase capacitance of collector current by applying the collector current of the power transistor in a vertical direction through a lower surface of a substrate. An integrated circuit includes a first conductive type high-density substrate(101), a first conductive type low-density epitaxial layer(102), a second conductive type low-density epitaxial layer(103), at least one small signal transistor(110), and at least one power transistor(120). The power transistor includes a base region(124) and an emitter region(125) formed on the second conductive type low-density epitaxial layer, and a collector region formed on the first conductive type high-density substrate. The small signal transistor includes a second conductive type first buried layer(111), a first conductive type second buried layer(112), a second conductive type third buried layer(113), a base region(114), an emitter region(115), and a collector region(116).
    • 提供一种具有功率晶体管及其制造方法的集成电路,通过在垂直方向上施加功率晶体管的集电极电流,从而提高集电极电流的电容。 集成电路包括第一导电型高密度衬底(101),第一导电型低密度外延层(102),第二导电型低密度外延层(103),至少一个小信号晶体管(110) )和至少一个功率晶体管(120)。 功率晶体管包括形成在第二导电型低密度外延层上的基极区域(124)和发射极区域(125)以及形成在第一导电型高密度衬底上的集电极区域。 小信号晶体管包括第二导电型第一掩埋层(111),第一导电型第二掩埋层(112),第二导电型第三掩埋层(113),基极区域(114),发射极区域(115) )和收集器区域(116)。
    • 6. 发明公开
    • 반도체 디바이스 및 보호 회로
    • 半导体器件和保护电路
    • KR1020080007137A
    • 2008-01-17
    • KR1020070070237
    • 2007-07-12
    • 르네사스 일렉트로닉스 가부시키가이샤
    • 다카하시유키오
    • H01L27/04
    • H01L27/0259H01L27/082
    • A semiconductor device and a protection circuit are provided to obtain an electrostatic discharge damage protection circuit having a high electrostatic discharge damage resistance without enlarging a layout size of the protection circuit. A well is formed in a region in which a protection circuit of an input/output terminal is arranged. A plurality of emitter diffusion layers are formed on the well and have a conductive type opposite to the conductive type of the well. A plurality of first collector diffusion layers are formed on the well and have a conductive type opposite to the conductive type of the well. A plurality of second collector diffusion layers are formed on the well and have a conductive type opposite to the conductive type of the well. A base diffusion layer is formed on the well and has the same conductive type as the conductive type of the well. An insulating layer is formed to isolate the emitter diffusion layers, the first collector diffusion layers, the second collector diffusion layers, and the base diffusion layer, respectively. A first bipolar transistor(10A) includes the emitter diffusion layers, the first collector diffusion layers, and the base diffusion layer. A second bipolar transistor(10B) includes the emitter diffusion layers, the second collector diffusion layers, and the base diffusion layer. A third bipolar transistor(10C) includes the first collector diffusion layers, the second collector diffusion layers, and the base diffusion layers. The emitter diffusion layers are electrically connected to the input/output terminal. The first collector diffusion layer is electrically connected to a first power supply terminal. The second collector diffusion layers and the base diffusion layer are electrically connected to a second power supply terminal.
    • 提供半导体器件和保护电路以获得具有高静电放电损伤电阻的静电放电损坏保护电路,而不增加保护电路的布局尺寸。 在其中布置有输入/输出端子的保护电路的区域中形成阱。 在阱上形成多个发射极扩散层,并具有与阱的导电类型相反的导电类型。 在阱上形成多个第一集电极扩散层,并具有与阱的导电类型相反的导电类型。 多个第二集电极扩散层形成在阱上并且具有与阱的导电类型相反的导电类型。 在阱上形成基极扩散层,并具有与导电类型相同的导电类型。 形成绝缘层以隔离发射极扩散层,第一集电极扩散层,第二集电极扩散层和基极扩散层。 第一双极晶体管(10A)包括发射极扩散层,第一集电极扩散层和基极扩散层。 第二双极晶体管(10B)包括发射极扩散层,第二集电极扩散层和基极扩散层。 第三双极晶体管(10C)包括第一集电极扩散层,第二集电极扩散层和基极扩散层。 发射极扩散层电连接到输入/输出端。 第一集电极扩散层与第一电源端子电连接。 第二集电极扩散层和基极扩散层与第二电源端子电连接。