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1. 发明专利

JP6314725B2 受信回路有权
公开(公告)号：JP6314725B2
公开(公告)日：2018-04-25
申请号：JP2014152942
申请日：2014-07-28
申请人：株式会社ソシオネクスト
发明人：森内恒彦 , 大澤宏充
IPC分类号： H03K5/08
CPC分类号： H03K3/012 , H03K3/356139 , H03K3/356191 , H03K5/2481 , H03K5/249

2. 发明专利

JP2004343396A Level shift circuit 审中-公开
公开(公告)号：JP2004343396A
公开(公告)日：2004-12-02
申请号：JP2003137124
申请日：2003-05-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHIKAWA TOMOYA , NAKAGAWA HIROBUMI
IPC分类号： G09G3/36 , G09G3/20 , H03K3/356 , H03K19/0185
CPC分类号： H03K3/356139 , H03K3/356191
摘要： PROBLEM TO BE SOLVED: To suppress the occurrence of a through current in a level shift circuit of CMOS constitution.
SOLUTION: To a level shift basic circuit 10 of the CMOS constitution composed of four transistors M1-M4, a control circuit 20 for suppressing the through current is added. While N type MOS transistors M7 and M8 for control are turned off by turning control input VS1 to an L level (a switch off period), two pieces of complementary data input Vin1 and Vin2 are shifted. In the switch off period, the respective sources of the N type MOS transistors M1 and M2 are cut off from a VSS. Also, during the switch off period, by turning the control input VS2 to the L level, P type MOS transistors M5 and M6 for the control are turned on. In the on period of the P type MOS transistors M5 and M6 for the control, two pieces of data output Vout1 and Vout2 are both precharged to a VDD (precharging period).
COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2010288016A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2010288016A
公开(公告)日：2010-12-24
申请号：JP2009139452
申请日：2009-06-10
申请人： Toshiba Corp , 株式会社東芝
发明人： TEH CHEN KONG , HARA HIROYUKI
IPC分类号： H03K3/356 , H01L21/822 , H01L27/04 , H03K5/13 , H03K19/0175 , H03K19/096
CPC分类号： H03K3/356191
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can secure sufficient delay time in a small area.
SOLUTION: The semiconductor integrated circuit device includes: first inverters (PT21, NT21) comprising a first transistor for performing charge to a charge point based on input and a second transistor for performing discharge from a discharge point based on the input; a P-type third transistor and an N-type fourth transistor (PT22, NT22) having drain-source paths formed in parallel to each other between the charge point and the discharge point; and a second inverter (INV21) for obtaining a delay signal of the input from the charge point or the discharge point by inverting the potential of the charge point or the discharge point to be supplied to the gates of the third and fourth transistors.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供可以在小区域中确保足够的延迟时间的半导体集成电路器件。解决方案：半导体集成电路器件包括：第一反相器（PT21，NT21），其包括用于基于输入对充电点进行充电的第一晶体管和用于基于输入从放电点进行放电的第二晶体管; 具有在充电点和放电点之间彼此平行地形成的漏极 - 源极路径的P型第三晶体管和N型第四晶体管（PT22，NT22）以及第二反相器（INV21），用于通过反转要提供给第三和第四晶体管的栅极的充电点或放电点的电位来获得来自充电点或放电点的输入的延迟信号。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2009118335A Latch circuit and flip-flop circuit 有权
标题翻译：锁存电路和FLIP-FLOP电路
公开(公告)号：JP2009118335A
公开(公告)日：2009-05-28
申请号：JP2007291060
申请日：2007-11-08
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H03K3/356
CPC分类号： H03K3/0375 , H03K3/356191
摘要： PROBLEM TO BE SOLVED: To reduce the generation rate of any soft error in a latch circuit.
SOLUTION: A latch circuit 10 includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits controls the voltage value of its own first node in accordance with the voltage value of any of the second modes. Each of the second node voltage control circuits controls the voltage value of its own second node in accordance with the voltage value of any of the first nodes.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：降低锁存电路中的任何软错误的产生速率。锁存电路10包括：三个以上的第一节点，并且第一信号电平中的电压被设置在该节点上; 设置三个以上的第二节点，并且通过反转第一信号电平而获得第二信号电平中的电压; 和具有第一节点的第一节点电压控制电路; 以及具有第二节点的第二节点电压控制电路。每个第一节点电压控制电路根据任何第二模式的电压值控制其自己的第一节点的电压值。每个第二节点电压控制电路根据任何第一节点的电压值来控制其自己的第二节点的电压值。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008211615A Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：JP2008211615A
公开(公告)日：2008-09-11
申请号：JP2007047407
申请日：2007-02-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , YAGYU MASAYOSHI , FUKUDA KOJI
IPC分类号： H03K3/356 , H03F3/34 , H03F3/45 , H03K3/3562
CPC分类号： H03K3/356191 , H03K3/356139 , H03K3/3562 , H03M9/00
摘要： PROBLEM TO BE SOLVED: To attain speeding up of various logic circuits, the one example of which is a latch circuit. SOLUTION: For example, configuration constituted of a data fetching part BF which fetches a data input signal Din by differential amplifier configuration when a clock signal CK is at an 'H' level and a latch part LT which latches a data output signal Dout from the BF when the CK is at the 'L' level is provided with a gain control part GCTL and common node control part CMNCTL. The GCTL is provided between common nodes COMN1 and COMN2 of NMOS transistors MN1, MN2 in a differential amplifier and has a function for making a gain of the differential amplifier higher in a high frequency band than in a low frequency band. The CMNCTL has a function for controlling electric charges so as to eliminate potential difference between the COMN1 and the COMN2 when the CK is at the 'L' level. Thus, transition time of the Dout is moved up and a setup margin in the LT is expanded. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了实现各种逻辑电路的加速，其一个例子是锁存电路。解决方案：例如，由时钟信号CK为“H”电平时通过差分放大器配置取出数据输入信号Din的数据取出部分BF构成的配置和锁存数据输出信号的锁存部分LT 当CK处于“L”电平时，从BF发出的Dout设置有增益控制部分GCTL和公共节点控制部分CMNCTL。 GCTL设置在差分放大器中的NMOS晶体管MN1，MN2的公共节点COMN1和COMN2之间，并且具有使高分辨率的差分放大器的增益高于低频带的功能。当CK处于“L”电平时，CMNCTL具有用于控制电荷的功能，以消除COMN1和COMN2之间的电位差。因此，Dout的转换时间向上移动，LT中的设置余量被扩展。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008085235A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008085235A
公开(公告)日：2008-04-10
申请号：JP2006266142
申请日：2006-09-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUOKA FUMIYOSHI , WATANABE YOJI , FUKUDA MAKOTO
IPC分类号： H01L21/8238 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/11 , H01L29/786
CPC分类号： H03K3/356191 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： PROBLEM TO BE SOLVED: To increase the soft error immunity of a semiconductor device.
SOLUTION: A semiconductor device comprises at least two inverter circuits consisting of a transistor of a second conductivity type that is formed by a diffusion layer of the second conductivity type formed in a semiconductor layer of a first conductivity type and a transistor of the first conductivity type that is formed by a diffusion layer of the first conductivity type formed in a semiconductor layer of the second conductivity type. The diffusion layer of the second conductivity type is divided into multiple regions by element isolation regions, and the multiple regions are connected by first metal wiring. The diffusion layer of the first conductivity type is divided into multiple regions by element isolation regions, and the multiple regions are connected by second metal wiring.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高半导体器件的软错误抗扰度。解决方案：半导体器件包括至少两个反相器电路，其由第二导电类型的晶体管组成，该晶体管由形成在第一导电类型的半导体层中的第二导电类型的扩散层和第一导电类型由形成在第二导电类型的半导体层中的由第一导电类型的扩散层形成。第二导电类型的扩散层通过元件隔离区分成多个区域，多个区域通过第一金属布线连接。第一导电类型的扩散层通过元件隔离区分成多个区域，多个区域通过第二金属布线连接。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005151438A Comparator circuit 有权
标题翻译：比较器电路
公开(公告)号：JP2005151438A
公开(公告)日：2005-06-09
申请号：JP2003389484
申请日：2003-11-19
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： WAKAMATSU TAKESHI , HORIKAWA SHIGEMITSU
IPC分类号： H03K5/08 , G01R19/00 , G11C7/00 , H03D1/00 , H03K3/356 , H03K5/24
CPC分类号： H03K5/2481 , H03K3/35613 , H03K3/356191 , H03K5/249
摘要： PROBLEM TO BE SOLVED: To provide a comparator circuit without causing any malfunction.
SOLUTION: This comparator circuit comprises: a differential amplifier circuit composed of differential paired transistors (M1, M2) for inputting signals to be compared and current mirror load circuits (M3, M4, M5, M6); a latch circuit composed of an inverted amplifier which is configured so that one input become the other output, in order to amplify differential output signals outputted from the current mirror load circuits in accordance with the relationship of magnitudes between the signals to be compared; an equalizing transistor (M9) for equalizing the signals of the differential amplifier circuit; delay circuits (M13, M14, M15, M16) for generating a signal that delays a control signal input to a control electrode of the equalizing transistor; and a control transistor (M10) wherein the output signal of the delay circuit is input to the control electrode as the control signal for activating/inactivating the latch circuit.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供比较器电路而不引起任何故障。该比较电路包括：用于输入要比较的信号的差分成对晶体管（M1，M2）和电流镜负载电路（M3，M4，M5，M6）组成的差分放大电路; 由反相放大器构成的锁存电路，该反相放大器被配置为使得一个输入成为另一个输出，以便根据要比较的信号之间的关系来放大从电流镜载入电路输出的差分输出信号; 均衡晶体管（M9），用于均衡差分放大器电路的信号; 延迟电路（M13，M14，M15，M16），用于产生延迟输入到均衡晶体管的控制电极的控制信号的信号; 以及控制晶体管（M10），其中延迟电路的输出信号作为用于激活/失活锁存电路的控制信号输入到控制电极。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2018026802A レベルシフタおよび電圧レベルをシフトする方法审中-公开
公开(公告)号：JP2018026802A
公开(公告)日：2018-02-15
申请号：JP2017122825
申请日：2017-06-23
申请人：ミニマプロセッサーオイ
发明人：パーシオアリ , コスキネンラウリ , トゥルンクイストマシュー
IPC分类号： H03K19/0185
CPC分类号： H03K19/0185 , H03K3/356113 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/018521 , H03K19/018585 , H03K19/0963
摘要：【課題】入力信号に基づいて出力信号を生成するための新規なレベルシフタを提供する。【解決手段】出力信号を高い電圧にセットするために出力端子205を第1の供給電圧VDDHに接続するための第1の制御スイッチ207、および出力信号を低いにセットするために出力端子を信号用アースGNDに接続するための第2の制御スイッチ208を備える。また、出力端子を第1の供給電圧に接続するためのプリチャージスイッチ210、および第2の制御スイッチを制御するために入力信号の能力を制御するための入力ゲート回路211を備える。更に、出力信号に基づいて第1の制御スイッチを制御するためのキーパー回路212を備える。第1の制御スイッチは、出力信号が低いときには第1の供給電圧によって制御され、そして出力信号が高いときには第1の供給電圧と信号用アースとの間にある第2の供給電圧によって制御される。【選択図】図2

9. 发明专利

JP2012090247A Level shift circuit and method of the same 审中-公开
标题翻译：水平移位电路及其方法
公开(公告)号：JP2012090247A
公开(公告)日：2012-05-10
申请号：JP2010275354
申请日：2010-12-10
申请人： Fitipower Integrated Technology Inc , 天▲ギョク▼科技股▲ふん▼有限公司
发明人： HWANG HONG-AN , LIU YUNG-YUAN
IPC分类号： H03K19/0185 , H03F1/02 , H03F3/45 , H03K3/356
CPC分类号： H03K3/356191 , H03K3/012
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit and a method of the same.SOLUTION: In a level shift circuit and a method of the same, a current-limiting circuit is connected between a latch device in the level shift circuit and a voltage source to limit a driving current for the latch device not to exceed a setting value. Thereby, a consumption current is reduced when the level shift circuit is converted, the latch device using a transistor with a shorter channel is realized, thus a level shift circuit area is reduced. By making the setting value adjustable to adjust an output driving capability of the level shift circuit, a conversion rate of the level shift circuit can be accelerated.
摘要翻译：要解决的问题：提供电平移位电路及其方法。解决方案：在电平移位电路及其方法中，限流电路连接在电平移位电路中的锁存装置和电压源之间，以限制锁存装置的驱动电流不超过设定值。因此，当电平移位电路被转换时，消耗电流减小，使用具有较短信道的晶体管的锁存器件实现了电平移位电路区域。通过使设定值可调以调整电平移位电路的输出驱动能力，可以加速电平移位电路的转换速率。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2009232184A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2009232184A
公开(公告)日：2009-10-08
申请号：JP2008075423
申请日：2008-03-24
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： TOMISATO SHIGEKI
IPC分类号： H03K5/08 , H03K17/00 , H03M1/12
CPC分类号： G11C27/026 , G11C7/16 , G11C27/024 , H03K3/012 , H03K3/356121 , H03K3/356191
摘要： PROBLEM TO BE SOLVED: To provide a circuit capable of accurately sampling an input signal potential for a post-stage circuit without being affected by mode switching of a dynamic comparator.
SOLUTION: A semiconductor integrated circuit is constituted of a comparator circuit wherein a sampling circuit (20) is connected between an input signal source (60) and a post-stage circuit (90), an input signal switch (30) is connected between the input signal source (60) and an input terminal (8) of a dynamic comparator (70), further, one terminal of a comparator capacitor (40) is connected between the input signal switch (30) and the input terminal (8), and another terminal thereof is connected to a fixed potential. A timing control circuit (50) outputs a control signal for bringing the input signal switch (30) into a cutoff state before switching the dynamic comparator from a standby mode to a comparison mode and outputs a control signal for ending sampling of the sampling circuit (20) after switching.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够精确地对后级电路的输入信号电位进行采样的电路，而不受动态比较器的模式切换的影响。解决方案：半导体集成电路由比较器电路构成，其中采样电路（20）连接在输入信号源（60）和后级电路（90）之间，输入信号开关（30）为连接在输入信号源（60）和动态比较器（70）的输入端子（8）之间，另外，比较电容器（40）的一个端子连接在输入信号开关（30）和输入端子 8），其另一端连接固定电位。定时控制电路（50）在将动态比较器从备用模式切换到比较模式之前输出用于使输入信号开关（30）进入截止状态的控制信号，并输出用于结束采样电路采样的控制信号（ 20）切换后。版权所有（C）2010，JPO＆INPIT

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