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1. 发明专利

JP2011015149A Waveform equalization circuit with pulse width modulation 有权
标题翻译：波形宽度调制的波形均衡电路
公开(公告)号：JP2011015149A
公开(公告)日：2011-01-20
申请号：JP2009157036
申请日：2009-07-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , FUKUDA KOJI
IPC分类号： H04L25/03 , H04B3/04
CPC分类号： H04B3/04
摘要： PROBLEM TO BE SOLVED: To achieve low power consumption of a waveform equalization circuit with pulse width modulation.SOLUTION: There is provided: pulse width adjustment level generation circuits PWCLC1a and PWCLC2a that generate a pulse width adjustment level VCNT based on previous input data Din_P and Din_N; pulse width adjustment circuits PWCC1a and PWCC2a that adjust the pulse width depending on the VCNT; and a waveform shaping circuit WAC that shapes an output signal waveform from the pulse width adjustment circuits. In the pulse width adjustment circuit, the driving power is controlled according to consecutive bits count of the previous input data, and varies transition time of output data Do2_P and Do2_N to adjust the pulse width. By using such a waveform equalization scheme, power consumption can be reduced due to simplification in circuit configuration, and further, CMOS circuits can keep the power small.
摘要翻译：要解决的问题：实现具有脉冲宽度调制的波形均衡电路的低功耗。提供：脉冲宽度调整电平生成电路PWCLC1a和PWCLC2a，其基于先前的输入数据Din_P生成脉宽调整电平VCNT， Din_N; 脉冲宽度调节电路PWCC1a和PWCC2a，根据VCNT调节脉冲宽度; 以及波形整形电路WAC，其对来自脉冲宽度调整电路的输出信号波形进行整形。在脉冲宽度调整电路中，根据先前输入数据的连续比特数来控制驱动功率，并且改变输出数据Do2_P和Do2_N的转换时间以调整脉冲宽度。通过使用这样的波形均衡方案，由于电路结构的简化，能够降低功耗，进一步地，CMOS电路可以保持功率小。

2. 发明专利

JP2005267700A Semiconductor integrated circuit and magnetic storage device using it 有权
标题翻译：半导体集成电路和使用它的磁存储器件
公开(公告)号：JP2005267700A
公开(公告)日：2005-09-29
申请号：JP2004075526
申请日：2004-03-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , YAGYU MASAYOSHI , YUKI FUMIO , KAWASHITA TATSUYA
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B5/39 , G11C16/06 , H03K17/00 , H03K17/687
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which enables the reduction of a circuit space, and a magnetic storage device using it.
SOLUTION: The semiconductor integrated circuit includes; an output transistor MN200 of a single stage configuration which supplies a write current nIw to a magnetic head 1; a current source 22 which outputs a current Iw to be used as a reference of the write current nIw; an NMOS transistor MN202 of diode connection which converts the current Iw to the gate voltage and is equipped with a constant element size ratio to the output transistor MN200; a regulator circuit 21 which transmits gate voltage of the NMOS transistor MN202, and makes the output impedance small; and a CMOS circuit 20 which makes the output of the regulator circuit 21 power source voltage and controls a gate voltage of the output transistor. These circuits are applied as write circuits of the magnetic storage device.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够减少电路空间的半导体集成电路和使用该半导体集成电路的磁存储装置。解决方案：半导体集成电路包括：向磁头1提供写入电流nIw的单级结构的输出晶体管MN200; 输出用作写入电流nIw的基准的电流Iw的电流源22; 二极管连接的NMOS晶体管MN202，其将电流Iw转换为栅极电压，并且与输出晶体管MN200配备有恒定的元件尺寸比; 调节电路21，其传输NMOS晶体管MN202的栅极电压，并使输出阻抗较小; 以及CMOS电路20，其使调节器电路21的输出电源电压并控制输出晶体管的栅极电压。这些电路被用作磁存储装置的写入电路。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2014002226A Optical communication device and information communication device 审中-公开
标题翻译：光通信设备和信息通信设备
公开(公告)号：JP2014002226A
公开(公告)日：2014-01-09
申请号：JP2012136502
申请日：2012-06-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , FUKUDA KOJI , YAMASHITA HIROKI , KATO TAKESHI
IPC分类号： G02B6/26
摘要： PROBLEM TO BE SOLVED: To solve the problem in which: a connection operation of insertion and withdrawal individually to a plurality of optical modules arranged on a substrate is very complicated in operating a device.SOLUTION: The present invention proposes a structure in which corresponding optical modules of a plurality of optical modules can be integrally optically coupled to each other so as to avoid convergence of edges of substrate wiring and improve throughput. Accordingly, even when the numbers of the optical modules increases on a single substrate, optical coupling can be performed in a short time without impairing maintainability. That is, as the optical modules can be moved integrally with a relay substrate, workability is improved and costs can be effectively reduced.
摘要翻译：要解决的问题：为了解决这样一个问题，其中：单独插入和取出布置在基板上的多个光学模块的连接操作在操作设备时非常复杂。解决方案：本发明提出了一种结构，其中相应的光学多个光学模块的模块可以彼此一体地光学耦合，以避免衬底布线的边缘的会聚并提高生产量。因此，即使在单个基板上的光模块的数量增加的情况下，也可以在短时间内进行光耦合，而不会损害可维护性。也就是说，随着光学模块能够与继电器基板一体地移动，可以提高可操作性并且可以有效地降低成本。

4. 发明专利

JP2005269336A Signal transmitter circuit, signal output circuit, and method of terminating signal transmission circuit 有权
标题翻译：信号发射机电路，信号输出电路和终止信号传输电路的方法
公开(公告)号：JP2005269336A
公开(公告)日：2005-09-29
申请号：JP2004080172
申请日：2004-03-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAGYU MASAYOSHI , YAMASHITA HIROKI , YUKI FUMIO , KAWASHITA TATSUYA
IPC分类号： H03K19/0175 , G05F1/40 , G05F1/44 , G05F1/618 , H04B1/38 , H04B1/44 , H04B3/02 , H04L25/02
CPC分类号： H04B3/02 , H04L25/0282
摘要： PROBLEM TO BE SOLVED: To provide a signal transmitter circuit, a signal output circuit and a method of terminating the signal transmitter circuit which prevents signals from re-reflecting at the transmit end of a transmission line, if the impedance of the signal output circuit differs from the characteristic impedance of the transmission line.
SOLUTION: The signal transmitter circuit is composed of a transmission line 21 a signal output circuit 20 connected to the transmit end ND20 of the transmission line 21, and a signal receiver circuit 22 connected to the receive end ND21 of the transmission line 21. To prevent output signals of a signal output unit 200 from re-reflecting at the transmit end ND20 through the receive end ND21 on the signal transmitter circuit, a correcting current generator 201 is provided for the transmit end ND 20 which outputs a correcting current I
CAN of a current density at a timing set by a current density/timing controller 201a.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供信号发送器电路，信号输出电路和终止信号发送器电路的方法，其防止信号在传输线的发射端处重新反射，如果信号的阻抗输出电路与传输线的特性阻抗不同。解决方案：信号发送器电路由连接到传输线21的发送端ND20的信号输出电路20的传输线21和连接到传输线21的接收端ND21的信号接收器电路22组成为了防止信号输出单元200的输出信号在发送端ND20通过信号发送器电路上的接收端ND21重新反射，为发送端ND20提供校正电流发生器201，发送端ND20输出校正电流I 在电流密度/定时控制器201a设定的时刻，电流密度的 CAN 。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2011221386A Optical transmission module and optical communication apparatus using the same 有权
标题翻译：光传输模块和光通信设备
公开(公告)号：JP2011221386A
公开(公告)日：2011-11-04
申请号：JP2010092069
申请日：2010-04-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , TSUJI SHINJI , SHINODA KAZUNORI
IPC分类号： G02B6/42 , H01S5/022 , H01S5/026 , H01S5/10
CPC分类号： G02B6/43 , G02B6/4204 , G02B6/4214 , G02B6/4249 , G02B6/4257 , G02B6/428 , H01L2224/16225 , H01L2924/15311 , H01S5/0224 , H01S5/02284 , H01S5/02288 , H01S5/02292 , H01S5/024
摘要： PROBLEM TO BE SOLVED: To improve a heat radiation property of an optical transmission module.SOLUTION: An optical element 20 which an optical transmission module comprises has a principal surface (a first principal surface) 20a which is a light receiving/emitting surface and a principal surface on the opposite side of the principal surface 20a (a second surface) 20b, and is mounted on a wiring board by a flip-chip connection method through a plurality of bump electrodes formed on the principal surface 20b. A lens (an optical lens) 12 is fixed to the principal surface 20a side of the optical element 20. A heat radiation block (a heat radiation member) 16 is fixed between the optical element 20 and the lens 12, and the undersurface of the heat radiation member (a first surface) 16a abuts on the principal surface 20a of the optical element 20.
摘要翻译：要解决的问题：提高光传输模块的散热性能。解决方案：光传输模块包括的光学元件20具有作为光接收/发射表面的主表面（第一主表面）20a和在主表面20a的相对侧上的主表面（第二主表面）表面）20b，并且通过倒装芯片连接方法通过形成在主表面20b上的多个凸块电极安装在布线板上。透镜（光学透镜）12固定在光学元件20的主表面20a侧。散热块（散热构件）16固定在光学元件20和透镜12之间，并且散热构件（第一表面）16a邻接光学元件20的主表面20a。（C）2012，JPO和INPIT

6. 发明专利

JP2008167094A Level conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：JP2008167094A
公开(公告)日：2008-07-17
申请号：JP2006353595
申请日：2006-12-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , YUKI FUMIO , NEMOTO AKIRA , KANAI HISAAKI , YAMAMOTO KEIICHI
IPC分类号： H03K19/0185 , H03K19/0948
CPC分类号： H03K19/094 , H03K19/018521
摘要： PROBLEM TO BE SOLVED: To provide a technique achieving a low power and a high-speed operation and being capable of inhibiting the fluctuation of input-output characteristics by a power-supply voltage, a temperature change and the dispersion or the like of device characteristics in a level conversion circuit.
SOLUTION: The level conversion circuit has a source follower circuit 603 with a transistor NM1 inputting an AC signal at a CML level and the transistor NM2 inputting a control voltage Vc and a control-voltage generating circuit 602 generating the control voltage Vc inputting the transistor NM2. The control-voltage generating circuit 602 has a replica source follower circuit 604 as a replica for the source follower circuit 603 with the transistor NM3 inputting a central voltage at the CML level and the transistor NM4 inputting the control voltage Vc. The control-voltage generating circuit 602 further has a comparator 605 controlling the control voltage Vc so that the output voltage of the replica source follower circuit 604 and a CMOS-circuit threshold voltage Vcmosth are equalized.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种实现低功率和高速操作的技术，并且能够通过电源电压，温度变化和分散等来抑制输入 - 输出特性的波动的电平转换电路中的器件特性。解决方案：电平转换电路具有源极跟随器电路603，其具有以CML电平输入AC信号的晶体管NM1和输入控制电压Vc的晶体管NM2和产生控制电压Vc输入的控制电压产生电路602 晶体管NM2。控制电压产生电路602具有作为源极跟随器电路603的复制品的复制源极跟随器电路604，其中晶体管NM3输入CML电平的中心电压和输入控制电压Vc的晶体管NM4。控制电压产生电路602还具有控制控制电压Vc的比较器605，使得复制源极跟随器电路604的输出电压和CMOS电路阈值电压Vcmosth相等。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2004180188A Data reproducing method and digital control type clock data recovery circuit 有权
公开(公告)号：JP2004180188A
公开(公告)日：2004-06-24
申请号：JP2002346767
申请日：2002-11-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , SONEHARA MICHIHITO
IPC分类号： H03L7/081 , H03L7/091 , H04J3/06 , H04L7/02 , H04L7/033
CPC分类号： H04L7/0331 , H03L7/0814 , H03L7/091 , H03L2207/50 , H04L7/0337
摘要： PROBLEM TO BE SOLVED: To expand a jitter tolerance (1), to expand a range where data can be acquired when a wander occurs (2), to improve the followability of a reproduction clock to the wander (3) and to attain the low power consumption of a circuit (4). SOLUTION: Data 101 are compared with an edge position of a data obtaining clock (reproduction clock) 102. If the interval resulting from the comparison falls below a reference value, a clock edge is made far from a data edge. In addition, a synthesis circuit and the simultaneous on-control of two control signals of an 8-1 selector generate a clock of an N phase obtained by dividing one cycle into N parts from a reference clock 109 and select a data obtaining clock in the clock of the N phase. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2007096484A Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：JP2007096484A
公开(公告)日：2007-04-12
申请号：JP2005280233
申请日：2005-09-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI
IPC分类号： H03K19/096 , H03K3/356
CPC分类号： H03K3/356043 , H03K3/012
摘要： PROBLEM TO BE SOLVED: To speed up various logic circuits such as a flip-flop circuit. SOLUTION: The logic circuit disclosed herein includes, for example: a current source CC1 for generating a current I0+I when a control signal CS is at an 'H' level, and generating a current I0 when at an 'L' level; a current mirror circuit for mapping the current generated by the source CC1 and comprising MOS transistors M1, M2; and a current source CC2 connected to the transistor M2 and generating a current I0+I. Further, a current of a node COMN formed branched from a connection node between the transistor M2 and the source CC2 drives a logic section LC including a flip-flop circuit comprising, e.g. a differential amplifier. The logic section LC is deactivated because the current of the node COMN is zero when the control signal CS is at an 'H' level and active because the current of the node COMN is I when the control signal CS is at an 'L' level. The logic section LC in the active state processes a data input signal Din and produces a data output signal Dout. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：加速诸如触发器电路的各种逻辑电路。解决方案：本文公开的逻辑电路包括例如：当控制信号CS处于“H”电平时产生电流I0 + I的电流源CC1，当处于“L”时产生电流I0，水平; 用于映射由源CC1产生并包括MOS晶体管M1，M2的电流的电流镜电路; 以及连接到晶体管M2并产生电流I0 + I的电流源CC2。此外，从晶体管M2和源CC2之间的连接节点分支形成的节点COMN的电流驱动包括触发电路的逻辑部分LC，该触发器电路包括：差分放大器。由于当控制信号CS为“H”电平时，节点COMN的电流为零，因此当控制信号CS为“L”电平时，节点COMN的电流为I，因此逻辑部分LC被激活。处于活动状态的逻辑部分LC处理数据输入信号Din并产生数据输出信号Dout。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006252687A Magnetic recording system 审中-公开
标题翻译：磁记录系统
公开(公告)号：JP2006252687A
公开(公告)日：2006-09-21
申请号：JP2005068838
申请日：2005-03-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , YAGYU MASAYOSHI , KAWASHITA TATSUYA
IPC分类号： G11B5/09
CPC分类号： G11B5/486 , G11B5/484
摘要： PROBLEM TO BE SOLVED: To reduce an area or to save on power of a write system circuit by easily adjusting an overshoot of a write current pulse. SOLUTION: Between an output driver 10a provided with an impedance Z S and a magnetic recording head 12a, two or more kinds of transmission lines 11a, 11b and 11c having respectively different characteristic impedances are provided. The respective transmission lines 11a, 11b and 11c are formed so that their respective impedances Z 1 , Z n-1 , Z n (n≥2) on the magnetic recording head side 12a are larger than those on the output driver 10a side (Z 1 >Z n-1 >Z n ), and the impedance Z S of the output driver 10a is set to the characteristic impedance Z 1 of the transmission line 11a or larger. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过容易地调整写入电流脉冲的过冲来减小写入系统电路的面积或节省电力。解决方案：提供具有阻抗Z S 的输出驱动器10a和磁记录头12a之间，提供分别具有不同特性阻抗的两种或更多种传输线11a，11b和11c。相应的传输线11a，11b和11c形成为它们各自的阻抗Z 1 ，Z n-1 ，Z n 磁记录头侧12a的尺寸大于输出驱动器10a侧（Z 1 > Z n-1 > Z n ），并且输出驱动器10a的阻抗Z S 被设置为传输线11a的特性阻抗Z 1 或更大。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2008211615A Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：JP2008211615A
公开(公告)日：2008-09-11
申请号：JP2007047407
申请日：2007-02-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , YAGYU MASAYOSHI , FUKUDA KOJI
IPC分类号： H03K3/356 , H03F3/34 , H03F3/45 , H03K3/3562
CPC分类号： H03K3/356191 , H03K3/356139 , H03K3/3562 , H03M9/00
摘要： PROBLEM TO BE SOLVED: To attain speeding up of various logic circuits, the one example of which is a latch circuit. SOLUTION: For example, configuration constituted of a data fetching part BF which fetches a data input signal Din by differential amplifier configuration when a clock signal CK is at an 'H' level and a latch part LT which latches a data output signal Dout from the BF when the CK is at the 'L' level is provided with a gain control part GCTL and common node control part CMNCTL. The GCTL is provided between common nodes COMN1 and COMN2 of NMOS transistors MN1, MN2 in a differential amplifier and has a function for making a gain of the differential amplifier higher in a high frequency band than in a low frequency band. The CMNCTL has a function for controlling electric charges so as to eliminate potential difference between the COMN1 and the COMN2 when the CK is at the 'L' level. Thus, transition time of the Dout is moved up and a setup margin in the LT is expanded. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了实现各种逻辑电路的加速，其一个例子是锁存电路。解决方案：例如，由时钟信号CK为“H”电平时通过差分放大器配置取出数据输入信号Din的数据取出部分BF构成的配置和锁存数据输出信号的锁存部分LT 当CK处于“L”电平时，从BF发出的Dout设置有增益控制部分GCTL和公共节点控制部分CMNCTL。 GCTL设置在差分放大器中的NMOS晶体管MN1，MN2的公共节点COMN1和COMN2之间，并且具有使高分辨率的差分放大器的增益高于低频带的功能。当CK处于“L”电平时，CMNCTL具有用于控制电荷的功能，以消除COMN1和COMN2之间的电位差。因此，Dout的转换时间向上移动，LT中的设置余量被扩展。版权所有（C）2008，JPO＆INPIT

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