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1. 发明专利

JP2007280759A Electronic switching circuit 审中-公开
标题翻译：电子开关电路
公开(公告)号：JP2007280759A
公开(公告)日：2007-10-25
申请号：JP2006105356
申请日：2006-04-06
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H01H9/54 , H03K17/28 , H03K17/687
CPC分类号： H03K17/687
摘要： PROBLEM TO BE SOLVED: To reduce the number of parts of an electronic switching circuit.
SOLUTION: A resistor R1 is connected between a gate/source of PchTrP1, a resistor R2 is connected between the gate of the PchTrP1 and one end of a push button switch SW, a resistor R3 is connected between a drain of the PchTrP1 and the gate of NchTrN1, and a resistor R4 is connected between the gate/the source of the NchTrN1. The NchTrN1 connects the source to one end of a direct current electric source 11 and one end of a load 12, and connects the drain to the gate of the PchTrP1. The PchTrP1 connects the source to the other end of the direct current electric source 11, and connects the drain to the other end of the load 12. A capacitor C connects one end to the one end of the push button switch SW, and connects the other end to the one end of the direct current electric source 11. The push button switch SW connects the other end to the gate of the NchTrN1, and at every time an open/close operation is carried out, the PchTrP1 repeats conduction and non-conduction alternately.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少电子开关电路的部件数量。
解决方案：电阻器R1连接在PchTrP1的栅极/源极之间，电阻器R2连接在PchTrP1的栅极和按钮开关SW的一端之间，电阻器R3连接在PchTrP1的漏极之间 NchTrN1的栅极和电阻R4连接在NchTrN1的栅极/源极之间。 NchTrN1将源极连接到直流电源11的一端和负载12的一端，并将漏极连接到PchTrP1的栅极。 PchTrP1将源极连接到直流电源11的另一端，并将漏极连接到负载12的另一端。电容器C将一端连接到按钮开关SW的一端，并将另一端连接到直流电源11的一端。按钮开关SW将另一端连接到NchTrN1的栅极，并且在每次执行打开/关闭操作时，PchTrP1重复导通和非导通，交替传导。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006253375A Semiconductor integrated circuit device, and design method, apparatus, and program of 有权
标题翻译：半导体集成电路设备及其设计方法，设备和程序
公开(公告)号：JP2006253375A
公开(公告)日：2006-09-21
申请号：JP2005067127
申请日：2005-03-10
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H01L21/82 , G06F17/50 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/11807
摘要： PROBLEM TO BE SOLVED: To provide a design method and an apparatus for the same wherein a cell library resource is effectively utilized and a well potential ensures conversion from a cell of a power supply potential to a cell that supplies an arbitrary well potential.
SOLUTION: The cell includes, on the surface of a substrate, taps 106, 107 for supplying potentials of wells 101, 102 where active elements are formed, and source diffusion regions 103, 104 of an opposite conductivity type to the wells. The cell is input, and the taps of the cell are converted to the same conductivity type as the source diffusion regions into a source region to freely set the well potential of the cell to an arbitrary potential. When the cell includes short circuits 108, 109 between the taps and the source, and the short circuit is the diffusion region of the same conductivity type as the taps, the short circuit is converted to the same conductivity type as the source diffusion regions into a source region.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种设计方法和装置，其中有效地利用了单元库资源，并且阱电位确保了从电源电位的单元到提供任意阱电位的单元的转换。解决方案：电池在衬底的表面上包括用于提供形成有源元件的阱101,102的电位的阱106,107以及与阱相反的导电类型的源极扩散区103,104。单元被输入，并且单元的抽头被转换成与源扩散区域相同的导电类型到源区域中，以将单元的阱电势自由地设置为任意的电位。当电池单元包括抽头和源之间的短路108,109，并且短路是与抽头相同的导电类型的扩散区域时，短路被转换成与源扩散区相同的导电类型为源区。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2008219491A Master slave type flip-flop circuit and latch circuit 审中-公开
标题翻译：主从类型FLIP-FLOP电路和LATCH电路
公开(公告)号：JP2008219491A
公开(公告)日：2008-09-18
申请号：JP2007054382
申请日：2007-03-05
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI , NONAKA AKIRA
IPC分类号： H03K3/037 , H03K19/00 , H03K19/096
CPC分类号： H03K3/35625 , H03K3/35606
摘要： PROBLEM TO BE SOLVED: To stably hold data in a standby mode. SOLUTION: A clock input circuit 13 is provided with a NAND circuit NAND 0 to which power is supplied even in the standby mode and performs the gate control of a clock signal CK by a standby mode signal RET. When the standby mode signal RET is L (the standby mode), a clock signal C01 is maintained as H and a clock signal C02 is maintained as L irrespective of the HL of the clock signal CK. In addition, the power supply of an FA part in the clock input circuit 13 and an FB part in a slave latch circuit 12 is maintained and the power supply is intercepted in the other circuit. Consequently, data are held by a loop formed by a transfer gate circuit TG4 in which the clock signal C01 is H, the clock signal C02 is L and which is on in the slave latch circuit 12 and active inverter circuits INV5, INV6. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在待机模式下稳定地保持数据。解决方案：时钟输入电路13设置有即使在待机模式下也供电的NAND电路NAND0，并且通过待机模式信号RET执行时钟信号CK的门控制。当待机模式信号RET为L（待机模式）时，时钟信号C01保持为H，时钟信号C02保持为L，而与时钟信号CK的HL无关。此外，保持时钟输入电路13中的FA部分的电源和从锁存电路12中的FB部分的电源，并且在另一个电路中截断电源。因此，由时钟信号C01为H，时钟信号C02为L，从锁存电路12和有源反相器电路INV5，INV6为导通的传输门电路TG4形成的环路保持数据。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007027314A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2007027314A
公开(公告)日：2007-02-01
申请号：JP2005205676
申请日：2005-07-14
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To conduct layout wiring that insulation among wirings may be ensured.
SOLUTION: The semiconductor integrated circuit device includes a first wiring 11 that is supplied at a given voltage, a second wiring 12 of which voltage is over the given voltage and a third wiring 13 of which voltage is below the given voltage. It also includes the first wiring 11 that is supplied at a specified voltage, the second wiring 12 of which voltage is below the given voltage and the third wiring 13 of which voltage is over the given voltage. Then, the respective wirings are arranged at a wiring space (d) so that the first wiring 11 may be interposed between the second and third wirings 12 and 13. The wiring 11 of which potential difference is found to be small is always arranged adjoining to the wiring 12. Therefore, the wiring 13 of which potential difference from the wiring 12 may be large is hard to directly be adjoining to the wiring 12. Due to such the layout-based wiring, insulation among the wirings can be ensured enough.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：进行布线布线，可以确保布线之间的绝缘。解决方案：半导体集成电路器件包括以给定电压提供的第一布线11，电压超过给定电压的第二布线12和电压低于给定电压的第三布线13。它还包括以指定电压提供的第一布线11，其电压低于给定电压的第二布线12和电压超过给定电压的第三布线13。然后，将各个布线布置在布线空间（d）处，使得第一布线11可以插入在第二布线12和第三布线13之间。发现电位差小的布线11总是布置成邻近因此，与布线12的电位差可能较大的布线13难以直接与布线12相邻。由于这种基于布局的布线，可以确保布线之间的绝缘。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005242697A Method for verifying delay time 审中-公开
标题翻译：验证延迟时间的方法
公开(公告)号：JP2005242697A
公开(公告)日：2005-09-08
申请号：JP2004052048
申请日：2004-02-26
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI , KASHIWAGI YOSHIKI
IPC分类号： G06F17/50 , H01L21/82 , H04L12/26
CPC分类号： G06F17/5022
摘要： PROBLEM TO BE SOLVED: To provide a delay time verification method capable of verifying whether delay time in a section to be verified satisfies prescribed timing restriction or not even when the reverse phenomenon of a temperature characteristic appears.
SOLUTION: The delay time of the verification section is calculated by using a delay time MIN table 11 prepared at the minimum temperature in an operation guarantee range at first (step S11). Then the delay time of the verification section is calculated by using a delay time MIN table 12 prepared at the maximum temperature in the operation guarantee range (step S12). Then whether the delay time of the verification section satisfies the prescribed timing restriction or not is verified by using the shorter delay time out of the delay time calculated in the step S11 and the delay time calculated in the step S12 (step S13).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种延迟时间验证方法，即使当出现温度特性的反向现象时，能够验证待验证的部分中的延迟时间是否满足规定的时序限制。解决方案：首先通过使用在最低温度下制备的延迟时间MIN表11来计算验证部分的延迟时间（步骤S11）。然后，通过使用在操作保证范围内的最高温度下准备的延迟时间MIN表12来计算验证部的延迟时间（步骤S12）。然后，通过使用在步骤S11中计算的延迟时间中的较短的延迟时间和在步骤S12中计算的延迟时间来验证验证部分的延迟时间是否满足规定的时序限制。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004158631A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2004158631A
公开(公告)日：2004-06-03
申请号：JP2002322546
申请日：2002-11-06
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H04B3/36 , H04L25/24
CPC分类号： H04L25/24 , H04B3/36
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where signal delay time in signal wiring is shortened.
SOLUTION: A buffer 10 where two inverters are connected in series is inserted into signal wiring of the semiconductor device as a repeater. In the buffer 10, current driving capability of the invertor 11 in a pre-stage is set to be larger than that of the inverter 12 in a post-stage.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种其中信号布线中的信号延迟时间缩短的半导体器件。解决方案：将两个反相器串联连接的缓冲器10作为中继器插入到半导体器件的信号布线中。在缓冲器10中，在后级中将反相器11的前级的电流驱动能力设定为大于逆变器12的电流驱动能力。版权所有（C）2004，JPO

7. 发明专利

JP2009118335A Latch circuit and flip-flop circuit 有权
标题翻译：锁存电路和FLIP-FLOP电路
公开(公告)号：JP2009118335A
公开(公告)日：2009-05-28
申请号：JP2007291060
申请日：2007-11-08
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H03K3/356
CPC分类号： H03K3/0375 , H03K3/356191
摘要： PROBLEM TO BE SOLVED: To reduce the generation rate of any soft error in a latch circuit.
SOLUTION: A latch circuit 10 includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits controls the voltage value of its own first node in accordance with the voltage value of any of the second modes. Each of the second node voltage control circuits controls the voltage value of its own second node in accordance with the voltage value of any of the first nodes.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：降低锁存电路中的任何软错误的产生速率。锁存电路10包括：三个以上的第一节点，并且第一信号电平中的电压被设置在该节点上; 设置三个以上的第二节点，并且通过反转第一信号电平而获得第二信号电平中的电压; 和具有第一节点的第一节点电压控制电路; 以及具有第二节点的第二节点电压控制电路。每个第一节点电压控制电路根据任何第二模式的电压值控制其自己的第一节点的电压值。每个第二节点电压控制电路根据任何第一节点的电压值来控制其自己的第二节点的电压值。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008085571A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2008085571A
公开(公告)日：2008-04-10
申请号：JP2006262422
申请日：2006-09-27
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： YAMAMOTO HIROSHI
IPC分类号： H03K19/00 , H01L21/822 , H01L27/04
CPC分类号： G05F1/56 , H01L21/823412 , H03K17/063 , H03K17/687 , H03K19/0016 , H03K2017/066 , H03K2217/0018 , H03K2217/0036
摘要： PROBLEM TO BE SOLVED: To reduce a leakage current containing a sub-threshold leakage current and a substrate current. SOLUTION: A plurality of kinds of MIS transistors (LVT, MVT and HVT) having the same conductivity type and different threshold voltages are fitted to an internal circuit in a semiconductor integrated circuit. A power-switch transistor (31) interrupting a power supply to a certain functional block (10) in standby mode is fitted to the internal circuit. The MIS transistor (MVT) excepting the MIS transistor (HVT) having the highest threshold voltage in a plurality of kinds of the MIS transistors (LVT, MVT and HVT) is used as the power-switch transistor (31). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了减少包含亚阈值漏电流和衬底电流的漏电流。解决方案：具有相同导电类型和不同阈值电压的多种MIS晶体管（LVT，MVT和HVT）被安装在半导体集成电路中的内部电路中。在待机模式下中断向特定功能块（10）供电的电源开关晶体管（31）被安装到内部电路。使用在多个MIS晶体管（LVT，MVT和HVT）中具有最高阈值电压的MIS晶体管（HVT）之外的MIS晶体管（MVT）作为功率开关晶体管（31）。版权所有（C）2008，JPO＆INPIT

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