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1. 发明专利

JP2018093207A 結晶性半導体膜および板状体ならびに半導体装置审中-公开
公开(公告)号：JP2018093207A
公开(公告)日：2018-06-14
申请号：JP2017250270
申请日：2017-12-26
申请人：株式会社FLOSFIA
发明人：人羅俊実 , 織田真也 , 高塚章夫
IPC分类号： H01L29/872 , H01L29/06 , H01L29/24 , H01L29/78 , H01L29/12 , H01L29/861 , H01L29/868 , H01L29/739 , H01L21/336 , H01L21/338 , H01L29/778 , H01L29/812 , H01L21/337 , H01L29/808 , H01L29/786 , H01L21/28 , H01L29/47 , C23C16/40 , H01L33/26 , H01L21/368 , H01L21/365
CPC分类号： H01L29/24 , C23C16/40 , C23C16/4415 , C23C16/4481 , H01L21/0242 , H01L21/02565 , H01L21/02573 , H01L21/0262 , H01L21/02628 , H01L29/04 , H01L29/66969 , H01L29/739 , H01L29/7395 , H01L29/7722 , H01L29/778 , H01L29/7787 , H01L29/78 , H01L29/7827 , H01L29/8083 , H01L29/812 , H01L29/8122 , H01L29/872 , H01L29/8725 , H01L33/005 , H01L33/26 , H01L33/44
摘要：【課題】半導体特性、特に、リーク電流が抑制され、耐圧性および放熱性に優れている半導体膜および板状体ならびに半導体装置を提供する。【解決手段】コランダム構造を有する酸化物半導体を主成分として含む結晶性半導体膜、特に、ガリウム、インジウムおよびアルミニウムから選ばれる1種または2種以上の酸化物のうち、半導体である成分を主成分として含む結晶性半導体膜であって、膜厚が1μm以上であることを特徴とする結晶性半導体膜または板状体ならびに前記結晶性半導体膜または前記板状体を含む半導体構造を備える半導体装置。【選択図】なし

3. 发明专利

JP2009521816A The apparatus and method of fast recovery rectifier structure 有权
公开(公告)号：JP2009521816A
公开(公告)日：2009-06-04
申请号：JP2008548647
申请日：2006-12-20
申请人：キュースピードセミコンダクターインコーポレーテッド
发明人：ジョンソン，エリック , ファン，ヤン，ユー , フランシス，リチャード , ホアン，ハイ
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872 , H01L27/0641 , H01L27/0814 , H01L27/0817 , H01L29/0623 , H01L29/7722 , H01L29/8083 , H01L29/861 , H01L29/8725
摘要：高速回復整流器構造体の装置および方法。具体的には構造体は第１のドーパントの基板（１２０）を含む。第１のドーパントが低濃度ドープされた第１のエピタキシャル層（１４０）が基板に結合されている。第１の金属層（１９０）が第１のエピタキシャル層に結合されている。複数のトレンチ（１７５）が第１のエピタキシャル層内に窪んでおり、その各々が金属層と結合している。装置は各々第２のドーパント型がドープされた複数のウェルも含み、各ウェルは対応するトレンチの下に且つ隣接して形成されている。複数の酸化物層（１７０）が対応するトレンチの壁および底部上に形成されている。第１のドーパントがドープされた複数のチャネル領域が、２つの対応するウェル間の第１のエピタキシャル層内に形成されている。複数のチャネル領域（１５０）の各々は第１のエピタキシャル層より高濃度に第１のドーパントがドープされている。

4. 发明专利

JP4250144B2 Semiconductor device and manufacturing method thereof having a channel conduction region highly doped 有权
公开(公告)号：JP4250144B2
公开(公告)日：2009-04-08
申请号：JP2004569454
申请日：2003-03-19
申请人：サイスドエレクトロニクスデヴェロプメントゲゼルシャフトミットベシュレンクテルハフツングウントコンパニコマンディートゲゼルシャフト
发明人：エルペルト、ルドルフ , シェルナー、ラインホルト , ミットレーナー、ハインツ
IPC分类号： H01L21/337 , H01L21/04 , H01L29/06 , H01L29/10 , H01L29/24 , H01L29/739 , H01L29/772 , H01L29/78 , H01L29/80 , H01L29/808 , H01L29/812
CPC分类号： H01L29/1608 , H01L29/0634 , H01L29/1025 , H01L29/1029 , H01L29/1033 , H01L29/66053 , H01L29/66068 , H01L29/7392 , H01L29/7722 , H01L29/7828 , H01L29/8083 , H01L29/8122
摘要： The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel region (22) forms part of the first semiconductor region (2) and comprises a base doping. The current (I) in the channel region (22) can be influenced by means of at least one depletion zone (23, 24). The channel region (22) contains an n-conductive channel region (225) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region (225) is produced by ionic implantation in an epitaxial layer (262) that surrounds the channel region (22).

5. 发明专利

JP2007294716A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007294716A
公开(公告)日：2007-11-08
申请号：JP2006121760
申请日：2006-04-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ONOSE HIDEKATSU
IPC分类号： H01L29/80 , H01L21/337 , H01L27/095 , H01L29/808
CPC分类号： H01L29/8083 , H01L29/0692 , H01L29/1608 , H01L29/66409 , H01L29/7722
摘要： PROBLEM TO BE SOLVED: To provide a diode-contained junction FET capable of sustaining a blocking state even for a low gate bias, and providing a large saturation current.
SOLUTION: The junction FET comprises a drain layer of n
+ SiC substrate 10, a drift layer of n
- SiC layer 11 in contact with the drain layer, a source layer of n
+ SiC layer 12 formed on the drift layer, a channel region of a part of the drift layer with a trench groove formed from the source layer to the predetermined depth of the drift layer, and a gate region of a p-type polycrystal Si filling the trench groove. A p-emiiter of the diode is formed with a gate region of one side of the channel short circuited with the source electrode.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供即使对于低栅极偏压也能够保持阻塞状态并且提供大的饱和电流的二极管包含的结FET。解决方案：结FET包括n + SiC衬底10的漏极层，与漏极层接触的n + SP> -SOC层11的漂移层，在漂移层上形成的n + SP + + SiC层12的源极层，具有从源极层到漂移层的预定深度形成的沟槽的漂移层的一部分的沟道区域，以及填充沟槽的p型多晶Si的栅极区域。形成二极管的对流体，其沟道的一侧的栅极区域与源电极短路。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2006093382A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006093382A
公开(公告)日：2006-04-06
申请号：JP2004276565
申请日：2004-09-24
申请人： Denso Corp , Hitachi Ltd , 株式会社デンソー , 株式会社日立製作所
发明人： OYANAGI TAKASUMI , WATANABE TOKUO , SAKAKIBARA TOSHIO , YAMAMOTO TAKESHI , NAKAMURA HIROKI , MALHAN RAJESH KUMAR
IPC分类号： H01L27/095 , H01L21/822 , H01L21/8232 , H01L27/04 , H01L27/06 , H01L29/47 , H01L29/80 , H01L29/861 , H01L29/872
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which incorporates a temperature measuring diode that can be operated at a high temperature and which can be used under a high temperature environment.
SOLUTION: When a structure where grooves 110 and 111 are used for control regions 12 and 14 is adopted as an electrostatic induction transistor, a normally-off device can be obtained in accordance with a distance between control layers. Normally-off device is used as inter-element separation, and a hetero-junction diode 114 (or pn junction diode) is constituted of silicon carbide and polycrystalline silicon. Inter-element separation is realized by grounding a deep p-type third layer 30. The temperature measuring diode can be formed between an n-type fourth layer on an inner side and the other face of a substrate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种碳化硅半导体器件，其包含可在高温下操作并可在高温环境下使用的温度测量二极管。解决方案：当将控制区域12和14用作沟槽110和111的结构用作静电感应晶体管时，可以根据控制层之间的距离获得常关器件。正常关断器件用作元件间隔离，异质结二极管114（或pn结二极管）由碳化硅和多晶硅构成。通过使深p型第三层30接地来实现元件间分离。温度测量二极管可以形成在内侧的n型第四层和衬底的另一面之间。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2000077662A Semiconductor switching element 有权
标题翻译：半导体开关元件
公开(公告)号：JP2000077662A
公开(公告)日：2000-03-14
申请号：JP24804598
申请日：1998-09-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAO TSUTOMU , ONO TOSHIYUKI , ONOSE HIDEKATSU , OIKAWA SABURO
IPC分类号： H01L29/80 , H01L27/04 , H01L29/10 , H01L29/12 , H01L29/739 , H01L29/772 , H01L29/78
CPC分类号： H01L29/7395 , H01L29/1095 , H01L29/7722 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To control the high breakdown voltage and large current of a semiconductor switching element by forming a second-conductivity semiconductor layer which is connected with a source electrode between adjacent well layers, and making the total content of impurities in the semiconductor layer smaller than those of impurities in the well layers.
SOLUTION: In a parallel-plate single-crystal silicon carbide semiconductor substrate 1 having main surfaces on its top and bottom sides, a low-resistance n+-type drain layer 2 and an n--type drift layer 3 having higher resistance than the layer 2 has are laminated upon another. A plurality of high- concentration p+-type well layers 41 is provided in the drift layer 3 from one main surface of the substrate 1 and a high-concentration n+-type source layer 5 and a p--type layer 10 containing impurities at a total content which is lower than that of impurities in the p+-type well layer 41 are formed in each p+-type well layer 41. The p--type layer 10 is brought into contact with the p-type well layers 41 on both sides. Consequently, the switching of a switching element provided with a voltage clamping function under a high-breakdown voltage and large-current condition can be inhibited.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了通过形成与相邻阱层之间的源电极连接的第二导电半导体层来控制半导体开关元件的高击穿电压和大电流，并且使半导体层中的杂质的总含量小于阱层中的杂质。解决方案：在其顶表面和底面具有主表面的平行板单晶碳化硅半导体衬底1中，具有比层更高的电阻的低电阻n +型漏极层2和n型漂移层3 2已经层压在另一个上。多个高浓度p +型阱层41从衬底1的一个主表面和漂移层3中的高浓度n +型源极层5和含有杂质的p型层10提供。在p +型阱层41中形成低于p +型阱层41中的杂质的总含量.p型层10与两侧的p型阱层41接触。因此，可以抑制在高击穿电压和大电流条件下具有电压钳位功能的开关元件的开关。

8. 发明专利

JPS6194375A Superlattice pbt 失效
标题翻译：超级PBT
公开(公告)号：JPS6194375A
公开(公告)日：1986-05-13
申请号：JP21522484
申请日：1984-10-16
申请人： Nippon Telegr & Teleph Corp
发明人： SUSA NOBUHIKO , ADACHI SADAO
IPC分类号： H01L29/80 , H01L29/15 , H01L29/772
CPC分类号： H01L29/7722 , H01L29/155
摘要： PURPOSE:To improve high-speed response characteristics by forming multilayer AlxGa1-xAs layers in the direction vertical to the direction of traveling of carriers between an emitter and a collector and monotonously increasing an (x) value along the direction of traveling of carriers. CONSTITUTION:AlxGa1-xAs layer 6 are arranged in the direction vertical to the direction of traveling of carriers between an emitter 3 and a collector 4, an (x) value is increased monotonously with a separation along the direction of traveling of carriers from the emitter 3, and a base 2 is disposed in one AlxGa1-xAs layer. When the repeated period of the change of compositions extends over approximately 100-2,000Angstrom , two periods or more of the layers 6 can be introduced in a normal superlattice PBT (a high-speed base electrode buried transistor). Electrons are injected to the layers 6 from the discontinuous sections (the ends of each period) of conduction bands, and accelerated at DELTAEcproportional (x2-x1). Accordingly, when such period structure is formed, hot electrons are injected repeatedly even on a thick active layer (between the emitter and a base) completely burying a cavity on a Schottky electrode, thus resulting in the expectation of response at high speed.
摘要翻译：目的：通过在与发射极和集电极之间的载流子行进方向垂直的方向上形成多层Al x Ga 1-x As层，并沿着载流子行进方向单调增加（x）值，来提高高速响应特性。构成：Al x Ga 1-x As层6沿着与发射体3和集电体4之间的载流子的行进方向垂直的方向排列，（x）值随着载流子从发射极的行进方向的分离而单调增加 3，基底2设置在一个Al x Ga 1-x As层中。当组合物的改变的重复时间段延伸超过约100-2,000埃时，层6的两个周期或更长时间可以被引入正常的超晶格PBT（高速基极掩埋晶体管）中。电子从导带的不连续部分（每个周期的末端）注入层6，并以DELTAEc比例（x2-x1）加速。因此，当形成这样的周期结构时，即使在厚的有源层（发射极和基极之间）也重复注入热电子，从而完全将肖特基电极上的空穴埋入其中，从而导致高速响应的期望。

9. 发明专利

JPS6134980A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS6134980A
公开(公告)日：1986-02-19
申请号：JP15397284
申请日：1984-07-26
申请人： Kaoru Mototani , Junichi Nishizawa , Res Dev Corp Of Japan
发明人： NISHIZAWA JUNICHI , MOTOTANI KAORU
IPC分类号： H01L29/80 , H01L21/8222 , H01L27/06 , H01L27/08 , H01L27/082 , H01L29/10 , H01L29/205 , H01L29/43 , H01L29/772
CPC分类号： H01L29/7722 , H01L27/0605 , H01L29/1025 , H01L29/205 , H01L29/432
摘要： PURPOSE:To obtain a rapid and low-power semiconductor integrated circuit which can be highly integrated, by providing an integrated circuit whose load resistance is connected in series with a thermionic emitting SIT. CONSTITUTION:A thermionic emitting SIT30 having normally-OFF properties has a load resistance 31, an input terminal 20, a grounding terminal 21, an output terminal 22 and a power input 23. When the input is zero and when the thermionic emitting SIT30 is OFF, the level becomes high in the output terminal 22. When the input becomes high, the SIT30 is turned ON and the level becomes low in the output terminal 22. Thus, the SIT30 performs so-called invertor operation. The current flowing through the circuit depends on the value of the load resistance 31. For example, when VDD is 1V and the load resistance is 1kOMEGA, the current is on the order of 1mA. Accordingly, the ON voltage of the thermionic emitting SIT30 becomes very low.
摘要翻译：目的：通过提供负载电阻与热电子发射SIT串联连接的集成电路，获得可以高度集成的快速和低功耗半导体集成电路。构成：具有常关特性的热离子发射SIT30具有负载电阻31，输入端子20，接地端子21，输出端子22和电源输入23.当输入为零并且当热离子发射SIT30为OFF时，输出端子22的电平变高。当输入变为高电平时，SIT30导通，输出端子22的电平变低。因此，SIT30执行所谓的反相器操作。流过电路的电流取决于负载电阻31的值。例如，当VDD为1V，负载电阻为1kOMEGA时，电流约为1mA。因此，热离子发射SIT30的导通电压变得非常低。

10. 发明专利

JPS6134979A Thermionic emitting electrostatic induction transistor 失效
标题翻译：发热静电感应晶体管
公开(公告)号：JPS6134979A
公开(公告)日：1986-02-19
申请号：JP15396984
申请日：1984-07-26
申请人： Kaoru Mototani , Junichi Nishizawa , Res Dev Corp Of Japan
发明人： NISHIZAWA JUNICHI , MOTOTANI KAORU
IPC分类号： H01L29/80 , H01L29/43 , H01L29/772
CPC分类号： H01L29/7722 , H01L29/432
摘要： PURPOSE:To obtain a thermionic emitting SIT in which carriers can move at a thermionic speed without being subjected to scattering of a crystal lattice, by forming a gate of a semiconductor having a wider forbidden band than a channel while providing a space between the source and the gate less than the mean free path of the carriers. CONSTITUTION:In a compound semiconductor such as GaAs which cannot provide a good insulation film, a gate is not formed of GaAs but of a mixed crystal having a wider forbidden band than GaAs, for example of Ga1-xAlxAs so that the gate is similar to an insulated gate. Further, as shown in the drawing, a channel 2 is provided between a source 3 and a drain 1 so as to pass between gate regions 4. In the channel 2, the distance from the source 3 to the true gate 4 is smaller than a mean free path of electrons, so that an electrostatic transistor of thermionic-emitting type is obtained. The space between and the thickness of the gate regions and the impurity density in the channel region can be altered to provide an either normally-ON or normally-OFF operating transistor. The impurity is preferably undoped so as to inhibit the implantation of electrons.
摘要翻译：目的：为了获得其中载流子能够以热离子速度移动而不会受到晶格散射的热离子发射SIT，通过形成具有比沟道更宽的禁带宽度的半导体栅极，同时在源极和源极之间提供空间，门小于载体的平均自由路径。构成：在不能提供良好绝缘膜的化合物半导体例如GaAs中，栅极不由GaAs形成，而是具有比GaAs更宽的禁带宽度的混合晶体，例如Ga1-xAlxAs，使得栅极类似于绝缘门此外，如图所示，通道2设置在源极3和漏极1之间，以便在栅极区域4之间通过。在沟道2中，从源极3到真正栅极4的距离小于电子的平均自由程，从而获得热离子发射型的静电晶体管。可以改变栅极区域之间的间隙和沟道区域中的杂质浓度，以提供常开或常关的工作晶体管。杂质优选为未掺杂的，以便抑制电子的注入。

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