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1. 发明专利

JP2010165772A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010165772A
公开(公告)日：2010-07-29
申请号：JP2009005584
申请日：2009-01-14
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUCHIYA NORIHIKO , SAIDA SHIGEHIKO , UDO SUKEMUNE , NITTA SHINICHI
IPC分类号： H01L21/26 , H01L21/265 , H01L21/28 , H01L21/3205 , H01L21/324 , H01L21/8247 , H01L23/52 , H01L27/10 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for suppressing the occurrence of crystal defects of the semiconductor device.
SOLUTION: A trench for STI is formed on a wafer, and an insulating film is buried in the trench. Then, oxygen is introduced to the surface of the wafer. For introducing oxygen, RTO (Rapid Thermal Oxidation) is performed to the surface of the wafer in an atmosphere of 100% oxygen at 1,100°C for 60 seconds. After that, high-temperature annealing is performed. In an SRAM manufacturing step, the introduction of oxygen is performed before a high-temperature annealing step and an ion implanting step of source/drain sections with the risk of causing dislocation. Thus, the crystal strength of the wafer can be enhanced, and the dislocation caused by the annealing step and the ion implanting step can be suppressed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种制造用于抑制半导体器件的晶体缺陷发生的半导体器件的方法。解决方案：在晶片上形成用于STI的沟槽，并且绝缘膜被埋在沟槽中。然后，将氧气引入到晶片的表面。为了引入氧气，在1100℃的100％氧气氛中，对晶片的表面进行RTO（快速热氧化）60秒。之后，进行高温退火。在SRAM制造步骤中，在高温退火步骤和源极/漏极部分的离子注入步骤之前进行氧的引入具有引起位错的风险。因此，可以提高晶片的晶体强度，并且可以抑制由退火步骤和离子注入步骤引起的位错。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2007227953A Semiconductor wafer, manufacturing method thereof, method and device for manufacturing semiconductor device 有权
标题翻译：半导体晶体管及其制造方法，制造半导体器件的方法和器件
公开(公告)号：JP2007227953A
公开(公告)日：2007-09-06
申请号：JP2007096900
申请日：2007-04-02
申请人： Toshiba Corp , 株式会社東芝
发明人： IWASE MASAO , NITTA SHINICHI , MIYASHITA MORIYA , SUGAMOTO JIYUNJI , YAMADA KOREI , NAGANO HAJIME , TANZAWA KATSUJIRO , UDO SUKEMUNE , NADAHARA SOICHI , TSUCHIYA NORIHIKO , MATSUSHITA HIROSHI , USHIKU YUKIHIRO , ARIKADO TSUNETOSHI , OKUMURA KATSUYA
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To manufacture a semiconductor device of high throughput by suppressing variation in manufacture among wafers, using a circular wafer in which neither notch nor orientation flat is present. SOLUTION: A semiconductor wafer 60 comprises a wafer of which a first main surface on which a semiconductor element is formed is circular, a bevel part formed on the outer periphery of the wafer, and a reference ID mark 61 which is provided to the bevel part to show crystal orientation of the wafer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过抑制晶片之间的制造变化来制造高通量的半导体器件，使用其中不存在凹口和取向平面的圆形晶片。解决方案：半导体晶片60包括其上形成有半导体元件的第一主表面是圆形的晶片，形成在晶片的外周上的斜面部分和参考ID标记61，斜面部分显示晶片的晶体取向。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007180569A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007180569A
公开(公告)日：2007-07-12
申请号：JP2007032512
申请日：2007-02-13
申请人： Toshiba Corp , 株式会社東芝
发明人： SATO TSUTOMU , NAGANO HAJIME , MIZUSHIMA ICHIRO , YAMADA TAKASHI , UDO SUKEMUNE , NITTA SHINICHI
IPC分类号： H01L27/12 , H01L21/205 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which occurrence of crystal defects in the substrate is prevented by reducing the influence of the temperature difference between an SOI region or SON (Silicon-On-Nothing) region and silicon regions on the substrate caused by the heat absorption efficiency difference therebetween even if the substrate is rapidly heated and rapidly cooled.
SOLUTION: A silicon region 23B is formed on the semiconductor substrate, and surrounding the silicon region 23B, an SOI region 22 is formed on the semiconductor substrate via either an insulating film or an empty cavity. Furthermore, a silicon region 23A is formed surrounding the SOI region 22 on the semiconductor substrate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中通过减少SOI区域或SON（Silicon-On-Nothing）区域和硅区域之间的温度差的影响来防止衬底中的晶体缺陷的发生，即使基板被快速加热并迅速冷却，其由吸热效率差异引起的基板。解决方案：在半导体衬底上形成硅区域23B，并且围绕硅区域23B，通过绝缘膜或空腔在SOI衬底上形成SOI区域22。此外，在半导体衬底上形成围绕SOI区域22的硅区域23A。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2002353080A SEMICONDUCTOR WAFER, DEVICE FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR WAFER 审中-公开
公开(公告)号：JP2002353080A
公开(公告)日：2002-12-06
申请号：JP2001345984
申请日：2001-11-12
申请人： TOSHIBA CORP
发明人： IWASE MASAO , NITTA SHINICHI , MIYASHITA MORIYA , SUGAMOTO JIYUNJI , YAMADA KOREI , NAGANO HAJIME , TANZAWA KATSUJIRO , UDO SUKEMUNE , NADAHARA SOICHI , TSUCHIYA NORIHIKO , MATSUSHITA HIROSHI , USHIKU YUKIHIRO , ARIKADO TSUNETOSHI , OKUMURA KATSUYA
IPC分类号： H01L21/02 , H01L23/544
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which can adopt an optimum process for each wafer, in each manufacturing process. SOLUTION: A bevel part is made at the periphery of a wafer, a product is made on the wafer, an ID mark is given to the bevel part separately for each wafer, and the ID mark is read and a new product is made on the wafer, based on the information indicated in the ID mark. The ID mark shows the information about the product made on the wafer. This device can recognize the lot No. or the order of manufacture of a product made on the wafer, the function of the product, the inspection results of the manufacture process and others by reading the ID mark. The ID mark is given each time by a required number of times at manufacture process of each product, and it is referred to, when setting the manufacture conditions in the subsequent manufacture process.

5. 发明专利

JP2000266671A CRYSTAL DEFECT-DETECTING APPARATUS AND METHOD FOR DETECTING CRYSTAL DEFECT 失效
公开(公告)号：JP2000266671A
公开(公告)日：2000-09-29
申请号：JP6906499
申请日：1999-03-15
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： OBUCHI MASUMI , UDO SUKEMUNE
IPC分类号： G01B11/30 , C30B29/06 , C30B33/02 , C30B33/12 , G01N21/41 , G01N21/49 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To make accurately measurable the position and the size of crystal defects in a scattering light direction (Z direction). SOLUTION: The crystal defect-detecting apparatus at least includes one laser 1 for emitting a laser light 5 of an infrared range, a stage 11 where a sample 3 which is irradiated with the laser light 5, is placed, an image sensor 4 for detecting a scattering light 6 scattered by the sample 3, and a means for forming an irradiation shape of the laser light 5 to an ellipse having a major axis of a predetermined angle to a direction of the scattering light or a rectangle having a long side of a predetermined angle. The laser light 5 can be radiated with a scanning time shifted to crystal defects at different positions in the scattering light direction within a width of the laser light.

6. 发明专利

JP2000260840A METHOD AND DEVICE FOR MEASURING SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JP2000260840A
公开(公告)日：2000-09-22
申请号：JP6709999
申请日：1999-03-12
申请人： TOSHIBA CORP
发明人： UDO SUKEMUNE
IPC分类号： H01L21/027 , G03F7/20 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To avoid a leveling error in a scan type stepper by, at measuring flatness for examining an exposure focal point plane with a semiconductor substrate tilted, measuring the flatness of the semiconductor substrate for each measurement unit region whose area is that of an exposure unit region or less. SOLUTION: An exposure unit region has a horizontal length X mm and vertical length Y mm, while a measurement unit region is a region S21 having a horizontal length L1 mm which is a scanning direction for scan exposure and a vertical length L2 mm. LTV-measurement is performed for each measurement unit region S21 to determine a leveling reference plane for each measurement unit region S21, and the measurement unit region is sequentially shifted from S21a to S21b, and then to S21c for measurement likewise, determining a leveling reference plane. Related to shifting of measurement unit region, the measurement unit regions S21a and S21b, for example, as well as S21b and S21c, are performed to overlap by at least 1/2 of horizontal length. Thus, a high-precision leveling control is provided.

7. 发明专利

JP2001093868A METHOD FOR MANUFACTURING SILICON WAFER, AND SILICON WAFER 失效
公开(公告)号：JP2001093868A
公开(公告)日：2001-04-06
申请号：JP27218599
申请日：1999-09-27
申请人： TOSHIBA CORP
发明人： SUGAMOTO JIYUNJI , UDO SUKEMUNE
IPC分类号： H01L21/306 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a silicon wafer with smooth surfaces and a method of manufacturing such a silicon wafer, where the formation of particles is suppressed. SOLUTION: A silicon wafer 1 is subjected to a lapping step and an alkali etching step, after which the wafer 1 is subjected to a deposition step, wherein a wafer smoothing layer 2 is deposited on one of its surfaces, and then subjected to a mirror-finished surface step, where the other surface of the wafer 1 is mirror-surface finished. The layer 2 is preferably a polysilicon layer deposited by a CVD method, whereby fine asperities on the surface of the wafer 1 resulting from the alkali etching step are filled to obtain a planarized surface and to prevent the formation of particles in subsequent steps. The mirror-surface finished surface also allows the wafer 1 to be obtained, where the formation of particles is suppressed.

8. 发明专利

JP2003258212A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003258212A
公开(公告)日：2003-09-12
申请号：JP2002062512
申请日：2002-03-07
申请人： TOSHIBA CORP
发明人： SATO TSUTOMU , NAGANO HAJIME , MIZUSHIMA ICHIRO , YAMADA TAKASHI , UDO SUKEMUNE , NITTA SHINICHI
IPC分类号： H01L21/762 , H01L21/76 , H01L21/764 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/08 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce an influence of a temperature difference generated from the difference of thermal absorbing efficiencies of an SOI region or an SON region and a silicon region on a substrate even when abrupt heating or cooling is conducted on the substrate, and which can prevent a crystal defect from occurring on the substrate. SOLUTION: The semiconductor device comprises a first semiconductor layer 12 formed via either an insulating film or a cavity on a first region, and a plurality of second semiconductor layers 13 formed on a second region on the semiconductor substrate 11. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2001015420A SEMICONDUCTOR WAFER PATTERN EXPOSING METHOD AND PATTERN ALIGNER 失效
公开(公告)号：JP2001015420A
公开(公告)日：2001-01-19
申请号：JP18702999
申请日：1999-06-30
申请人： TOSHIBA CORP
发明人： UDO SUKEMUNE
IPC分类号： H01L21/027 , G03F9/00 , G03F9/02
摘要： PROBLEM TO BE SOLVED: To minimize generation of blurred patterns due to sagging of the outer regions of a wafer by setting the exposure focus plane by inclining the semiconductor wafer in such a way that the surface projections and depressions are minimum on the exposure focus plane in device area which is effective in an exposure unit area. SOLUTION: The leveling controlling means provided in a scanning stepper receives reflected light of laser light projected from a laser light source 17 to a wafer 1 by plural sensors 18, converts it into electric signals, judges if at least a part of a non effective chip area is included or not in an exposure unit area. If it is included, the leveling controlling means selects a part of sensors 18 corresponding to the effective chip area, processes the output signals of the selected sensors for measuring distance, calculates the reference plane by a reference calculating means 19, controls a wafer inclination controlling mechanism 20 according to the calculated reference plane for controlling the inclination of a stage 15 (inclination of the wafer 1) and the height of the stage 15 if necessary.

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