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    • 1. 发明专利
    • Manufacturing method of semiconductor device
    • 半导体器件的制造方法
    • JP2007324620A
    • 2007-12-13
    • JP2007204066
    • 2007-08-06
    • Toshiba Corp株式会社東芝
    • TSUCHIYA NORIHIKOUSHIKU YUKIHIROMIKATA YUICHIKAWASAKI ATSUKOUMEZAWA KAORI
    • H01L21/336H01L29/78
    • PROBLEM TO BE SOLVED: To suppress the expansion of dislocation generated by the activate annealing of a high concentration impurity region by decreasing stress generated at a pattern edge periphery without performing long time activation heat treatment at a high temperature.
      SOLUTION: In the formation of source-drain region of a MOS transistor with LDD structure, after forming a gate electrode 103 via a gate insulating film 102 on a p-type silicon substrate 101, ion implantation is performed using the gate electrode 103 or the like as an ion implantation mask, furthermore, an n-low concentration impurity region 106 is formed by heat treatment. Furthermore, a gate electrode side wall 104 adjacent to the gate electrode is formed. A source-drain region 108 is formed by forming an n+high concentration impurity region 107 by the ion implantation using the gate electrode side wall 104 as the ion implantation mask. Furthermore, an SiN film 109 is formed at a location adjacent to a first gate electrode side wall 104. After that, the activation heat treatment of the source-drain region 108 is performed.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 解决的问题为了通过降低在图案边缘周围产生的应力而抑制高浓度杂质区域的活化退火产生的位错扩大,而不进行高温下的长时间活化热处理。 解决方案:在具有LDD结构的MOS晶体管的源极 - 漏极区的形成中,在p型硅衬底101上经由栅极绝缘膜102形成栅电极103之后,使用栅电极 103等作为离子注入掩模,此外,通过热处理形成n低浓度杂质区域106。 此外,形成与栅电极相邻的栅电极侧壁104。 通过使用栅电极侧壁104作为离子注入掩模通过离子注入形成n +高浓度杂质区107来形成源极 - 漏极区108。 此外,在与第一栅电极侧壁104相邻的位置处形成SiN膜109.之后,进行源极 - 漏极区108的活化热处理。 版权所有(C)2008,JPO&INPIT
    • 2. 发明专利
    • Process control system, process control method, and manufacturing method of electronic device
    • 过程控制系统,过程控制方法和电子设备的制造方法
    • JP2007088035A
    • 2007-04-05
    • JP2005272019
    • 2005-09-20
    • Toshiba Corp株式会社東芝
    • SUGAMOTO JIYUNJIUSHIKU YUKIHIRO
    • H01L21/02H01L21/027
    • PROBLEM TO BE SOLVED: To provide a process control system capable of improvements of process capability and manufacturing yield.
      SOLUTION: The system comprises a monitoring unit 18 for monitoring apparatus information of a manufacturing apparatus 16; an apparatus information collecting unit 10 for collecting monitored values of the apparatus information from the monitoring unit 18 in the course of execution of a manufacturing process; a correlation creating unit 11 for creating a correlation with a monitored value of the apparatus information, a processing parameter for controlling the manufacturing apparatus 16, and a feature amount obtained from a finished shape in a manufacturing process for a test wafer; a process management unit 12 for calculating a set value of the processing parameter of the manufacturing process on the basis of at least one of estimated values of feature amounts calculated on the basis of a correlation with respect to each of monitored values excepting the monitored values of the apparatus information in a manufacturing process for a plurality of reference wafers; an apparatus control unit 20 for controlling the manufacturing apparatus in accordance with a processing recipe where set values are described in processing steps.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供能够改善工艺能力和制造产量的工艺控制系统。 解决方案:该系统包括用于监视制造装置16的装置信息的监视单元18; 用于在执行制造过程的过程中从监视单元18收集设备信息的监视值的装置信息收集单元10; 相关制造单元11,用于产生与装置信息的监视值的相关性,用于控制制造装置16的处理参数,以及在测试晶片的制造过程中从最终形状获得的特征量; 过程管理单元12,用于基于除了监视值的监视值之外的每个监视值的基于相关性计算的特征量的估计值中的至少一个来计算制造过程的处理参数的设定值 在多个参考晶片的制造过程中的装置信息; 装置控制单元20,用于根据在处理步骤中描述设定值的处理配方控制制造装置。 版权所有(C)2007,JPO&INPIT
    • 3. 发明专利
    • Process control system, process control method and method of manufacturing electronic apparatus
    • 过程控制系统,过程控制方法和制造电子设备的方法
    • JP2007005367A
    • 2007-01-11
    • JP2005180659
    • 2005-06-21
    • Toshiba Corp株式会社東芝
    • SUGAMOTO JIYUNJIUSHIKU YUKIHIROAKIYAMA KAZUTAKAHARAKAWA SHOICHI
    • H01L21/02G05B19/418H01L21/3065H01L21/8242H01L27/108H01L29/78
    • Y02P90/12Y02P90/20
    • PROBLEM TO BE SOLVED: To provide a process control system capable of improving process capability and production yield. SOLUTION: The system is provided with a client computer 15 for creating a correspondence relation between a monitoring value of information about a manufacturing apparatus and feature amount to be acquired from a control parameter of the manufacturing apparatus and a finished shape in a reference manufacturing process, in the reference manufacturing process; production management system 14 for creating a processing recipe describing a control parameter calculated, based on the dimensions of a processing object structure of an actual manufacturing process, as a first set value of a first step in an actual manufacturing process; apparatus information collecting section 32 for collecting monitoring values of the apparatus information from the manufacturing apparatus, currently executing the actual manufacturing process at the first set value; feature amount calculating section 36 for calculating feature amount corresponding to the monitoring value, on the basis of the correspondence relation; parameter calculating section 38 for calculating a second set value of a second step, subsequent to the first step on the basis of the feature amount; and apparatus control unit 19 for changing the processing recipe by using a the second set value as a set value of the second step. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供能够提高处理能力和生产产量的过程控制系统。 解决方案:系统设置有客户端计算机15,用于根据制造装置的控制参数和参考中的最终形状来创建关于制造装置的信息的监视值和要获取的特征量之间的对应关系 制造过程中,在参考制造过程中; 生产管理系统14,用于基于实际制造过程的处理对象结构的尺寸,将实际制造过程中的第一步骤的第一设定值计算出的描述控制参数的处理配方; 装置信息收集部分32,用于收集来自制造装置的装置信息的监视值,当前以第一设定值执行实际制造过程; 特征量计算部36,用于基于对应关系计算与监视值对应的特征量; 参数计算部38,用于基于特征量计算第一步骤之后的第二步骤的第二设定值; 以及用于通过使用第二设定值作为第二步骤的设定值来改变处理配方的设备控制单元19。 版权所有(C)2007,JPO&INPIT
    • 6. 发明专利
    • SEMICONDUCTOR DEVICE
    • JP2003179228A
    • 2003-06-27
    • JP2002297066
    • 2002-10-10
    • TOSHIBA CORP
    • USHIKU YUKIHIRO
    • H01L21/28H01L21/336H01L29/423H01L29/49H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device that has a fine MOS transistor where a thin gate oxide film is used, a source/drain region is formed by self alignment, and a shallow channel has a gate length of 0.5 μm or less. SOLUTION: On a semiconductor substrate 1, a gate insulating film 6, a gate electrode 7 formed on the gate insulating film 6, a thermal oxide film 2 formed on a source/drain region 4, and an insulating film 5 formed on the thermal oxide film are formed. The height of the upper surface of the insulating film is nearly the same as that of the upper surface of the gate electrode on the gate insulating film, and the thermal oxide film is thicker than the gate insulating film. An element can be flattened. In the semiconductor device, a dummy gate is used a mask for forming the source/drain region in a self- alignment manner, and at the same time the gate electrode is formed in self- alignment manner, thus forming the fine element without generating matching deviation between the source/drain region and gate electrode. COPYRIGHT: (C)2003,JPO
    • 7. 发明专利
    • SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
    • JPH06326102A
    • 1994-11-25
    • JP13539893
    • 1993-05-13
    • TOSHIBA CORP
    • IIJIMA TADASHIONO TOSHIKOUSHIKU YUKIHIRO
    • H01L21/3205H01L23/52
    • PURPOSE:To realize a practical low-resistance metallic wiring instead of an Al wiring by laminating a first metal film and a second metal film composed mainly of silver on a semiconductor substrate and forming a protective film containing the same metal as the first metal film to cover the surface of the second metal film. CONSTITUTION:An SiO2 film 2 is formed on a semiconductor substrate 1, and a groove for a buried wiring is formed in the SiO2 film 2. Then, a TiN film 3, a Ti film 4 and an Ag film 5 are formed sequentially on the whole face of the SiO2 film 2. Then, the TiN film 3, the Ti film 4 and the Ag film 5 in parts other than the groove part are removed, and a buried Ag wiring layer is formed. After that, an annealing operation is performed in an Ar gas atmosphere at 600 deg.C for 30 minutes, and a TiO2 film 6 is formed on the surface of the Ag film 5. Lastly, an interlayer insulating film 7 is deposited on the whole face, and the buried wiring is finished. Thereby, it is possible to restrain Ag from agglomerating in the Ag film 5, and wiring which utilizes the low resistivity of Ag can be obtained.