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1. 发明专利

JP2005209694A Method for recognizing id mark for semiconductor wafer 有权
标题翻译：用于识别半导体波形的标识符的方法
公开(公告)号：JP2005209694A
公开(公告)日：2005-08-04
申请号：JP2004011812
申请日：2004-01-20
申请人： Toshiba Corp , 株式会社東芝
发明人： IWASE MASAO
IPC分类号： H01L21/02 , G11B7/085 , G11B7/24 , H01L23/544
CPC分类号： H01L23/544 , H01L2223/54413 , H01L2223/54433 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To analogize and recognize an ID mark incapable of being recognized, and to improve the yield of a manufacturing process for a semiconductor. SOLUTION: The basic data of the ID mark for a semiconductor wafer are prestored in a memory 9 for a host computer 2, and the ID mark for the semiconductor wafer is read by an ID-mark recognizing device 1. When the read ID mark can be recognized, an information displaying the recognition of the ID mark is related to the basic data of the wafer in the memory 9. When the ID mark cannot be recognized, the ID mark for the wafer is stored in a recognition-error bit data storage section 6 for an ID-mark analogizing recognizing section 5 as recognition-error bit data, and a rate of concordance with the basic data, to which the information in the memory 9 is not associated, and the recognition-error bit data are computed by a comparison functional section 8. The basic data having the maximum rate of concordance are analogized as the ID mark, and the basic data satisfying a specified criterion are regarded as the ID mark for the wafer in this case. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了模拟和识别不能被识别的ID标记，并且提高半导体制造工艺的产量。解决方案：将半导体晶片的ID标记的基本数据预先存储在用于主计算机2的存储器9中，并且通过ID标记识别装置1读取半导体晶片的ID标记。当读取可以识别ID标记，显示ID标记的识别的信息与存储器9中的晶片的基本数据相关。当不能识别ID标记时，将晶片的ID标记存储在识别误差用于ID标记类比识别部分5的位数据存储部分6作为识别错误位数据，以及与存储器9中的信息不相关联的基本数据的一致率，以及识别错误位数据由比较功能部分8计算。具有最大一致性速率的基本数据被类比为ID标记，并且在这种情况下，满足特定标准的基本数据被认为是晶片的ID标记。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JPH09199719A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09199719A
公开(公告)日：1997-07-31
申请号：JP783596
申请日：1996-01-19
申请人： TOSHIBA CORP
发明人： MURAKOSHI ATSUSHI , IWASE MASAO , INABA SATOSHI , SUGURO KYOICHI , KITAURA YOSHIAKI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To make it possible to form a high-quality diffusion layer of a shallow junction easily by activating first and second second-conductivity type impurities by heat treatment, and forming a second conductivity type diffusion layer on the surface of a first-conductivity type semiconductor region. SOLUTION: With a gate electrode 4 as a mask, Ga is ion-implanted into the surface of an n-type silicon substrate 1, and a first impurity region 5a in an amorphous state is formed. Following this, BFz is ion-implanted into the surface of the n-type silicon substrate l with the gate electrode 4 used as a mask, a second impurity region 5b is formed on the surface of the first impurity region 5a. Next a silicon oxide film 6 as a layer insulating film is formed on the whole surface by atmospheric CVD, and the n-type silicon substrate 1 is heat-treated after that, and impurities are activated and crystal recovery of the first and second region 5a, 5b is performed and p-type source/drain diffusion layers 7 are formed. Consequently, it becomes possible to form heavily doped, shallow p-type source/drain diffusion layer 7.

3. 发明专利

JPS62273773A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62273773A
公开(公告)日：1987-11-27
申请号：JP11467786
申请日：1986-05-21
申请人： TOSHIBA CORP
发明人： IWASE MASAO
IPC分类号： H01L29/78 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To obtain an element having a channel width, which is more minute than the size of a mask, by etching a polycrystalline silicon film and a first insulating film, removing resist, thereafter forming a second insulating film on the entire surface, and performing anisotropic etching so that the second insulating film remains at the side wall of an element forming region. CONSTITUTION:A first insulating film 2 is formed on a silicon substrate 1. A polycrystalline film 3 is deposited on an LPCVD method. A resist pattern 4 is formed. Then the polycrystalline silicon film 3 and the first insulating film 2 are etched. The resist pattern 4 is removed. A CVD silicon oxide film 5 is deposited by a well known CVD method. The silicon oxide film 5 is made to remain on the side wall of an element forming region by anisotropic etching. A gate insulating film 6 is formed. At the same time, an interlayer insulating film 7 and a gate electrode 8 are formed. Thereafter, a diffused layer 9 is formed by an ion implantation method. After a third insulating film 10 is formed, a contact hole is formed in the gate electrode 8 and the diffused layer 9. Then a conductive film 11 is deposited.

4. 发明专利

JPH06204456A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06204456A
公开(公告)日：1994-07-22
申请号：JP34784992
申请日：1992-12-28
申请人： TOSHIBA CORP
发明人： IWASE MASAO
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L29/43 , H01L29/78 , H01L29/46 , H01L21/90
摘要： PURPOSE:To provide a semiconductor device wherein even when its size is reduced largely its short channel effect can be suppressed, and it can be operated with an excellent high-speed performance. CONSTITUTION:A semiconductor device wherein both source and drain electrodes 19a, 19b are formed respectively in the higher positions than the interface between a gate insulation film 13 and a gate electrode 14, and grooves are formed respectively in both source and drain diffusion layers, and further, metallic films 26, 26 are formed respectively in the grooves.

5. 发明专利

JP2013175605A Manufacturing method for nonvolatile semiconductor memory device and nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件和非易失性半导体存储器件的制造方法
公开(公告)号：JP2013175605A
公开(公告)日：2013-09-05
申请号：JP2012039327
申请日：2012-02-24
申请人： Toshiba Corp , 株式会社東芝
发明人： KUBOI SHUICHI , IGUCHI SUNAO , IWASE MASAO , MATSUDA TORU
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66666 , H01L27/11582 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a nonvolatile semiconductor memory device capable of performing etching processing excellent in shape controllability, and further to provide the nonvolatile semiconductor memory device.SOLUTION: A manufacturing method for a nonvolatile semiconductor memory device comprises the steps of: forming oxide layers among electrode layers and layers to be etched at any sides of upper sides and lower sides of the electrode layers and forming a laminate while alternately laminating the electrode layers and the layers to be etched; forming grooves passing through the laminate in a lamination direction; embedding insulators into the grooves; forming holes passing through the laminate in the lamination direction; selectively removing the layers to be etched via the holes; forming charge storage layers inside the holes; and forming channel body layers inside the charge storage layers.
摘要翻译：要解决的问题：提供一种能够进行形状可控性优异的蚀刻处理的非易失性半导体存储器件的制造方法，并且还提供非易失性半导体存储器件。解决方案：一种用于非易失性半导体存储器件的制造方法包括以下步骤在电极层的上侧和下侧的任何一侧的电极层和被蚀刻层之间形成氧化物层，并且在交替层叠电极层和被蚀刻层的同时形成层压体; 在层叠方向上形成通过所述层叠体的槽; 将绝缘子嵌入槽中; 在层叠方向上形成穿过层叠体的孔; 通过孔选择性去除待蚀刻的层; 在孔内形成电荷存储层; 以及在电荷存储层内形成通道体层。

6. 发明专利

JP2008311312A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008311312A
公开(公告)日：2008-12-25
申请号：JP2007155614
申请日：2007-06-12
申请人： Toshiba Corp , 株式会社東芝
发明人： IWASE MASAO , IGUCHI SUNAO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11531 , H01L27/11548
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a lower gate electrode of a peripheral circuit portion that is thicker than a lower gate electrode of a memory cell portion, establishes the stability of the electrical characteristics of a memory cell transistor and the stability of the operation of a peripheral circuit transistor, and is reduced in size at microlevel and is highly integrated.
SOLUTION: According to the semiconductor device, a first insulating film 2 is formed in a memory cell formation region 6 and a peripheral circuit formation region 7 of a semiconductor layer 1. A first electrode layer 3 is so formed on the first insulating film 2 that the first electrode layer 3 is thicker in the region 6 than in the region 7. A plurality of element isolating regions 5 are formed in the regions 6 and 7. A second insulating film 8 is formed on respective element isolating regions 5 and on the first electrode layer 3. A second electrode layer 12 is formed on the second insulating layer 8, and part of the second electrode layer 12 is buried in openings 11a and 11b, which penetrate the second insulating film 8 to reach the inside of the first electrode layer 3 in the regions 6 and 7, so that the second electrode layer 12 is connected electrically to the first electric layer 3.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供具有比存储单元部分的下栅电极厚的外围电路部分的下栅电极的半导体器件，建立了存储单元晶体管的电特性的稳定性以及外围电路晶体管的操作的稳定性，并且在微小尺寸上被减小并且高度集成。解决方案：根据半导体器件，在半导体层1的存储单元形成区域6和外围电路形成区域7中形成第一绝缘膜2.第一绝缘膜3形成在第一绝缘层第一电极层3在区域6中比在区域7中更厚的膜2.在区域6和7中形成有多个元件隔离区域5.第二绝缘膜8形成在各个元件隔离区域5和在第二绝缘层8上形成第二电极层12，并且第二电极层12的一部分被埋在开口11a和11b中，该开口11a和11b穿过第二绝缘膜8到达内部区域6和7中的第一电极层3，使得第二电极层12电连接到第一电层3.版权所有：（C）2009，JPO＆INPIT

7. 发明专利

JP2004200635A Semiconductor wafer and manufacturing method of the semiconductor wafer 有权
公开(公告)号：JP2004200635A
公开(公告)日：2004-07-15
申请号：JP2003092737
申请日：2003-03-28
申请人： Toshiba Corp , 株式会社東芝
发明人： IWASE MASAO , NADAHARA SOICHI
IPC分类号： H01L21/02 , H01L23/544 , H01L29/06
CPC分类号： H01L23/544 , H01L29/0657 , H01L2223/54413 , H01L2223/54433 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor wafer which can keep high visibility of an ID mark and enables consistent production control of a manufacturing process of a semiconductor device, and its manufacturing method. SOLUTION: The semiconductor wafer has opposed first and second major surfaces 12a, 12b, first and second bevel parts 13a, 13b provided to an outer circumferential part of the first and second major surfaces 12a, 12b respectively, a first recess 16 formed in a part of the first bevel part 13a and a first ID mark 17 attached to the bottom of the first recess and constituted of a projecting first dot. COPYRIGHT: (C)2004,JPO&NCIPI

8. 发明专利

JPH09139511A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH09139511A
公开(公告)日：1997-05-27
申请号：JP5628196
申请日：1996-03-13
申请人： TOSHIBA CORP
发明人： MURAKOSHI ATSUSHI , KOIKE MITSUO , SUGURO KYOICHI , ASAISHI TADAYUKI , IWASE MASAO
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L29/45 , H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To increase the activation concentration of an imputity diffusion layer, and realize low resistance contact with metal. SOLUTION: In the surface of an Si substrate 1, an impurity diffusion layer 4a is formed with which an Al electrode 6 is in contact from above. The surface layer 4a contains Ge concentration of at least 1×10 cm as impurities for changing the lattice constant, in the thermally non-equilibrium state. The lattice constant of the surface layer 4a is set larger than that of Si containing the same concentration Ge in the thermal equilibrium state. Thereby the height of a Schottky barrier of a contact formed between the surface layer 4a and the electrode 6 is decreased. The surface layer 4a contains electrically active B as impurities for imparting carriers. The concentration of B is higher than or equal to the solubility limit in the thermal equilibrium state in Si. By containing Ge, the mobility of the carrier in the surface layer 4a becomes larger than the mobility in Si.

9. 发明专利

JPH0225067A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0225067A
公开(公告)日：1990-01-26
申请号：JP17392088
申请日：1988-07-14
申请人： TOSHIBA CORP
发明人： IWASE MASAO , FUKUDA SANAE
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/786
摘要： PURPOSE:To obtain a MISFET of a surface conductivity type by a method wherein a P layer, an SiO2 layer, and gate electrode are laminated on an SiO2 film formed on an Si substrate, a P layer is formed on both the sides of the gate electrode, and an n layer is deposited on the P layer. CONSTITUTION:A single crystal Si 22 is laminated on an SiO2 film 21 formed on an Si substrate 20 and left unremoved in islands, and B ions are implanted into the island-like Si 22 to form a P layer 22a. Then an Si gate electrode 24 is formed thereon through the intermediary of a gate insulating film 23. Next, a P source 25 and a drain 26 are provided through the implantation of B ions, and then an N source 27 and a drain 28 are formed by the implantation of As ions. The Si substrate 20 treated so far is covered with a CVD SiO2 film 29 and an opening is provided thereto and a metal wiring is buried in it. Provided that the thickness of the P layer 22 is W, a Fermienergy difference between the P layer 22 and the substrate 20 denotes VFB, the dielectric constant of the P layer 22 is represented by epsilon, the concentration of impurity is expressed as CSUB, the thickness of the film is TBOX, and a potential and electrons, which do not make the surface of the P layer 22 on the substrate 20 side inverted, are VSUB and q, W is so set as not to exceed VFB.epsilonOX/q.CSUB.TBOX, when VSUB=0. By a structure mentioned above, a device composed of FETs of P-channel and n-channel, which is small in occupied area and who se conductance and threshold value are easily controlled, can be obtained.

10. 发明专利

JPS62150885A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62150885A
公开(公告)日：1987-07-04
申请号：JP29072985
申请日：1985-12-25
申请人： TOSHIBA CORP
发明人： IWASE MASAO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
摘要： PURPOSE:To reduce a parasitic capacity that hinders the microminiaturization of elements by forming a gate electrode, source, drain contact and source.drain electrodes with one mask pattern by self-aligning technique to eliminate the necessity of positioning margin between the patterns. CONSTITUTION:When a polycrystalline silicon film 5 is isotropically etched with a resist pattern 6 as a mask, the film 5 is sidewisely etched, and a region 7 becomes later source.drain contact. When an aluminum film 8 is removed together with the pattern 6 after the entire surface is further covered with the aluminum film 8, an aluminum film 8' remains only on a gate electrode. Then, with the films 5 and 8' as masks a nitride film 4 is etched, and source.drain 9 are formed by an ion implanting method or a thermal diffusing method. Further, a gate insulating film 3 of a source.drain contact 7 is removed by etching, and a tungsten film 10 is selectively deposited by a CVD method only on the contact 7 and the film 5.

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