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1. 发明专利

JP2013045953A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013045953A
公开(公告)日：2013-03-04
申请号：JP2011183788
申请日：2011-08-25
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYATA TOSHINORI , AOKI NOBUTOSHI
IPC分类号： H01L21/336 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/28114 , H01L21/76802 , H01L21/76838 , H01L29/512 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7831
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a gate electrode which includes a plurality of electrode layers with different work functions, has a low gate resistance, and can be manufactured easily.SOLUTION: According to an embodiment, a semiconductor device comprises: a substrate; and a gate insulating film formed on the substrate. The device further comprises: a gate electrode including a first electrode layer formed on an upper surface of the gate insulating film and having a first work function, and a second electrode layer continuously formed on the upper surface of the gate insulating film and an upper surface of the first electrode layer and having a second work function different from the first work function; and a sidewall insulating film formed on a sidewall of the gate electrode. In the device, a height of the upper surface of the first electrode layer is less than a height of an upper surface of the sidewall insulating film.
摘要翻译：解决的问题：为了提供包括具有不同功函数的多个电极层的栅电极的半导体器件，具有低栅极电阻，并且可以容易地制造。解决方案：根据实施例，半导体器件包括：衬底; 以及形成在基板上的栅极绝缘膜。该器件还包括：栅电极，包括形成在栅极绝缘膜的上表面上并具有第一功函数的第一电极层，以及连续地形成在栅极绝缘膜的上表面上的第二电极层，并具有与第一功函数不同的第二功函数; 以及形成在栅电极的侧壁上的侧壁绝缘膜。在该装置中，第一电极层的上表面的高度小于侧壁绝缘膜的上表面的高度。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2013069977A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013069977A
公开(公告)日：2013-04-18
申请号：JP2011208913
申请日：2011-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYANO KIYOTAKA , MIYATA TOSHINORI
IPC分类号： H01L21/336 , H01L21/20 , H01L21/265 , H01L29/78
CPC分类号： H01L29/66356 , H01L21/26506 , H01L21/324 , H01L29/165 , H01L29/7391
摘要： PROBLEM TO BE SOLVED: To provide a method for simply manufacturing a semiconductor device which can inhibit an off-leak current while achieving a high on-state current.SOLUTION: A semiconductor device manufacturing method comprises: forming a gate insulation film on a semiconductor substrate; forming a gate electrode on the gate insulation film; introducing a first conductivity type impurity to a drain layer formation region; subsequently, performing a heat treatment to activate the first conductivity type impurity in the drain layer formation region; subsequently, introducing an inactive impurity to a source layer formation region to make single crystals of the semiconductor substrate in the source layer formation region be amorphous; subsequently, introducing a second conductivity type impurity to the source layer formation region; and subsequently, irradiating microwave on the semiconductor substrate to mono-crystallize an amorphous semiconductor at least in the source layer formation region and to activate the second conductivity type impurity in the source layer formation region. A depth of the second conductivity type impurity in the source layer formation region is shallower than a depth of the first conductivity type impurity in the drain layer formation region.
摘要翻译：要解决的问题：提供一种简单地制造可以在实现高导通电流的同时抑制漏电流的半导体器件的方法。解决方案：半导体器件制造方法包括：在半导体衬底上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 向漏层形成区域引入第一导电型杂质; 随后进行热处理以激活漏层形成区域中的第一导电类型杂质; 随后，将不活泼杂质引入源层形成区域，以使源层形成区域中的半导体衬底的单晶为无定形的; 随后，向源极层形成区域引入第二导电型杂质; 然后在半导体衬底上照射微波，至少在源极层形成区域中单晶化非晶半导体，并激活源极层形成区域中的第二导电型杂质。源极层形成区域中的第二导电型杂质的深度比漏极层形成区域中的第一导电类型杂质的深度浅。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2015056619A 半導体装置有权
标题翻译：半导体器件
公开(公告)号：JP2015056619A
公开(公告)日：2015-03-23
申请号：JP2013190889
申请日：2013-09-13
申请人：株式会社東芝 , Toshiba Corp
发明人： KONDO YOSHIYUKI , GOTO MASAKAZU , KAWANAKA SHIGERU , MIYATA TOSHINORI
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66977 , H01L29/165 , H01L29/66356 , H01L29/66659 , H01L29/7391 , H01L29/7833
摘要：【課題】電源電圧を低く抑えることができるトンネル型半導体装置を提供する。【解決手段】本実施形態による半導体装置は、半導体層を備える。ゲート絶縁膜は、半導体層表面上に設けられている。ゲート電極は、半導体層上にゲート絶縁膜を介して設けられている。第1導電型のドレイン層は、ゲート電極の一端側にある半導体層内に設けられている。第2導電型のソース層は、ゲート電極の他端側および該ゲート電極の下側にある半導体層内に設けられている。ゲート電極の下側においてソース層の不純物濃度は略均一である。ゲート電極およびドレイン層には同一符号の電圧が印加される。【選択図】図1
摘要翻译：要解决的问题：提供一种允许降低电源电压的隧道半导体器件。解决方案：半导体器件包括半导体层。在半导体层的表面上设置栅极绝缘膜。栅电极经由栅极绝缘膜设置在半导体层上。第一导电型漏极层设置在位于栅电极的一端侧的半导体层中。第二导电型源极层设置在位于栅极电极的另一端侧的半导体层中，位于取向电极下方。源极层的杂质浓度基本上均匀地位于栅电极下方。具有相同极性的电压施加到栅极电极和漏极层。

4. 发明专利

JP2014041974A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014041974A
公开(公告)日：2014-03-06
申请号：JP2012184474
申请日：2012-08-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SOTOZONO AKIRA , KONDO YOSHIYUKI , MIYATA TOSHINORI
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78 , H01L29/0843 , H01L29/1025 , H01L29/66356 , H01L29/66477 , H01L29/7391
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that includes a region having a steep variation in impurity concentration in a position being in contact with a source diffusion layer and to provide a method of manufacturing the same.SOLUTION: A semiconductor device comprises: a substrate; and a gate electrode formed on the substrate via a gate insulating film. The device further comprises: a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type, each of which is formed on a surface of the substrate so as to sandwich the gate electrode; and a junction formation region formed between the source diffusion layer and the drain diffusion layer so as to be in contact with the source diffusion layer. The junction formation region comprises: a source extension layer of the first conductivity type; a pocket layer of the second conductivity type formed above the source extension layer; and a diffusion prevention layer formed between the source extension layer and the pocket layer, containing carbon, and preventing diffusion of an impurity between the source extension layer and the pocket layer.
摘要翻译：要解决的问题：提供一种半导体器件，其包括在与源极扩散层接触的位置中具有陡峭的杂质浓度变化的区域，并提供其制造方法。解决方案：半导体器件包括：基质; 以及通过栅极绝缘膜形成在基板上的栅电极。该器件还包括：第一导电类型的源极扩散层和第二导电类型的漏极扩散层，其每一个形成在衬底的表面上以夹持栅电极; 以及形成在源极扩散层和漏极扩散层之间以与源极扩散层接触的结形成区域。结形成区域包括：第一导电类型的源极延伸层; 形成在源极延伸层上方的第二导电类型的袋层; 以及形成在所述源延伸层和所述袋层之间的包含碳的扩散防止层，并且防止杂质在源延伸层和袋层之间的扩散。

5. 发明专利

JP2013105838A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013105838A
公开(公告)日：2013-05-30
申请号：JP2011247644
申请日：2011-11-11
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYATA TOSHINORI
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a tunnel off-leak current of a tunnel transistor.SOLUTION: According to one embodiment, a semiconductor device comprises a substrate and a gate electrode formed on the substrate via a gate insulating film. The semiconductor device further comprises a source region of a first conductivity type and a drain region of a second conductivity type being a conductivity type opposite to the first conductivity type both of which are formed so as to interpose the gate electrode therebetween in the substrate. In addition, the gate electrode has a first region of the first conductivity type formed at a source region side in the gate electrode and a second region which is formed at a drain region side in the gate electrode and has a smaller value obtained by subtracting an impurity concentration of the second conductivity type from an impurity concentration of the first conductivity type in comparison with that of the first region.
摘要翻译：要解决的问题：提供能够减少隧道晶体管的隧道泄漏电流的半导体器件。解决方案：根据一个实施例，半导体器件包括通过栅极绝缘膜形成在衬底上的衬底和栅电极。半导体器件还包括第一导电类型的源极区域和与第一导电类型相反的导电类型的第二导电类型的漏极区域，两者都形成为将栅极电极插入其中。此外，栅电极具有形成在栅极电极的源极侧的第一导电类型的第一区域和形成在栅极电极的漏极区侧的第二区域，并且具有通过减去栅极电极与第一导电类型的杂质浓度相比，第二导电类型的杂质浓度与第一导电类型的杂质浓度相比较。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012146817A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012146817A
公开(公告)日：2012-08-02
申请号：JP2011003907
申请日：2011-01-12
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYATA TOSHINORI , KAWANAKA SHIGERU , ADACHI KANNA
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/772 , H01L29/0895 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/6656 , H01L29/7836
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving MOSFET characteristics and to provide a method of manufacturing the same.SOLUTION: A semiconductor device according to the present invention comprises: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed by a channel-layer material having a wider band gap than a material of the substrate, under the gate insulating film; a source region and a drain region formed in the substrate along the channel direction so as to sandwich the channel layer; and a source extension layer that is formed in the substrate between the channel layer and the source region so as to overlap the side end portion of the channel layer at the source side, and that forms with the channel layer a heterointerface in which carriers tunnel.
摘要翻译：要解决的问题：提供能够改善MOSFET特性并提供其制造方法的半导体器件。解决方案：根据本发明的半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极下方的栅极绝缘膜; 由栅极绝缘膜下方的沟道层材料形成的沟道层材料具有比衬底材料更宽的带隙; 源极区域和漏极区域，沿着沟道方向形成在衬底中，以夹持沟道层; 以及源极延伸层，其形成在沟道层和源极区域之间的衬底中，以与源极侧的沟道层的侧端部重叠，并且与沟道层形成载流子隧道的异质界面。版权所有（C）2012，JPO＆INPIT

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