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1. 发明专利

JP2013115329A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2013115329A
公开(公告)日：2013-06-10
申请号：JP2011261995
申请日：2011-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSAKA TOMOMI , KONDO MASAKI , AOKI NOBUTOSHI , IZUMIDA TAKASHI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/4916 , H01L29/66825 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To improve both characteristics of writing operation and erasing operation.SOLUTION: A nonvolatile semiconductor memory device includes: a semiconductor substrate 11; a gate insulating film 12 that is formed on the semiconductor substrate; a floating gate electrode 13 that is formed on the gate insulating film, is composed of polysilicon containing a p-type impurity that is a group 13 element, and has a lower film 13a and an upper film 13b stacked on the lower film; an inter-electrode insulating film 16 that is formed on the floating gate electrode; and a control gate electrode 17 that is formed on the inter-electrode insulating film. The impurity concentration or the activation concentration of the p-type impurity in the upper film is higher than the impurity concentration or the activation concentration of the p-type impurity in the lower film.
摘要翻译：要解决的问题：提高写入操作和擦除操作的特性。解决方案：非易失性半导体存储器件包括：半导体衬底11; 形成在半导体基板上的栅极绝缘膜12; 形成在栅极绝缘膜上的浮栅电极13由包含作为13族元素的p型杂质的多晶硅构成，并且具有层叠在下膜上的下膜13a和上膜13b; 形成在浮栅上的电极间绝缘膜16; 以及形成在电极间绝缘膜上的控制栅电极17。上层膜中p型杂质的杂质浓度或活化浓度高于下层膜中p型杂质的杂质浓度或活化浓度。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2011253881A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011253881A
公开(公告)日：2011-12-15
申请号：JP2010125739
申请日：2010-06-01
申请人： Toshiba Corp , 株式会社東芝
发明人： OIKE NOBORU , KUSAKA TOMOMI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/26506 , H01L21/2652 , H01L21/76224 , H01L27/11521 , H01L27/11524 , H01L29/105 , H01L29/1054 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which suppresses diffusion of impurities included in an element region.SOLUTION: The nonvolatile semiconductor memory device includes a substrate 101 and a well region 102 formed in the substrate 101. The device includes a plurality of element regions 103 sectioned by element isolation grooves T formed in the well region 102 in such a way as to extend in a first direction parallel to a principal surface of the substrate and be adjacent to each other in a second direction perpendicular to the first direction, and an element isolation insulation film 104 embedded in the element isolation grooves T for isolating the element regions 103 from each other. The device further includes a first diffusion suppression layer 111, formed in the plurality of element regions 103 in such a way as to divide each of the plurality of element regions 103 into an upper element region 103A and a lower element region 103B, for suppressing diffusion of impurities implanted into the well region 102, and a second diffusion suppression layer 112 formed on a side face in a direction perpendicular to the second direction of the upper element region 103A for suppressing diffusion of the impurities.
摘要翻译：解决的问题：提供一种抑制元件区域中所含杂质扩散的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括衬底101和形成在衬底101中的阱区102.器件包括多个元件区103，元件区103由形成在阱区102中的元件隔离槽T分开，以这种方式以在平行于基板的主表面的第一方向上延伸并且在垂直于第一方向的第二方向上彼此相邻;以及元件隔离绝缘膜104，其嵌入元件隔离槽T中，用于隔离元件区域 103彼此。该装置还包括形成在多个元件区域103中的第一扩散抑制层111，以便将多个元件区域103中的每一个分成上部元件区域103A和下部元件区域103B，以抑制扩散注入到阱区域102中的杂质和形成在与上部元件区域103A的第二方向垂直的方向的侧面上的第二扩散抑制层112，以抑制杂质的扩散。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011114057A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011114057A
公开(公告)日：2011-06-09
申请号：JP2009267236
申请日：2009-11-25
申请人： Toshiba Corp , 株式会社東芝
发明人： KANEMURA TAKAEI , KUSAKA TOMOMI , IZUMIDA TAKASHI , KONDO MASAKI , AOKI NOBUTOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883 , G11C16/0441 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that improves charge retention properties of cell transistors while increasing a writing and erasing speeds.
SOLUTION: The semiconductor memory device is equipped with: a substrate 101; a first gate insulating film 111 formed on the substrate and serving as an FN tunneling film, a first floating gate 112 formed on the first gate insulating film; a second gate insulating film 113 formed on the first floating gate and serving as an FN tunneling film; a second floating gate 114 formed on the second gate insulating film; an intergate insulating film 115 formed on the second floating gate and serving as a charge blocking film; and a control gate 116 formed on the intergate insulating film. At least one of the first and second floating gates includes a metal layer.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高单元晶体管的电荷保持性能同时增加写入和擦除速度的半导体存储器件。解决方案：半导体存储器件配备有：衬底101; 形成在基板上并用作FN隧道膜的第一栅极绝缘膜111，形成在第一栅极绝缘膜上的第一浮动栅112; 形成在第一浮栅上并用作FN隧道膜的第二栅极绝缘膜113; 形成在第二栅极绝缘膜上的第二浮栅114; 形成在第二浮栅上并用作电荷阻挡膜的隔间绝缘膜115; 以及形成在隔间绝缘膜上的控制栅极116。第一和第二浮动栅极中的至少一个包括金属层。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011114034A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011114034A
公开(公告)日：2011-06-09
申请号：JP2009266591
申请日：2009-11-24
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMIDA TAKASHI , KUSAKA TOMOMI , KONDO MASAKI , AOKI NOBUTOSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11531 , H01L29/42332 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which miniaturizes each memory cell while suppressing degradation of a characteristic of the semiconductor memory device.
SOLUTION: The semiconductor memory device includes: a substrate 101; gate insulating films 111 formed on the substrate and each functioning as an FN (Fowler-Nordheim) tunneling film; first floating gates 112 formed on the gate insulating films; first inter-gate insulating films 113 formed on the first floating gates and each functioning as an FN tunneling film; second floating gates 114 formed on the first inter-gate insulating films; a second inter-gate insulating film 115 formed on the second floating gates and functioning as a charge blocking film; and a control gate 116 formed on the second inter-gate insulating film.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种能够抑制半导体存储装置的特性劣化的各存储单元的小型化的半导体存储装置。解决方案：半导体存储器件包括：衬底101; 栅极绝缘膜111，其形成在基板上并且各自用作FN（Fowler-Nordheim）隧穿膜; 形成在栅绝缘膜上的第一浮栅112; 第一栅极绝缘膜113，其形成在第一浮栅上并且各自用作FN隧道膜; 形成在第一栅极间绝缘膜上的第二浮栅114; 形成在第二浮动栅极上并用作电荷阻挡膜的第二栅极间绝缘膜115; 以及形成在第二栅极间绝缘膜上的控制栅极116。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2010161259A Process simulation program, process simulation method, process simulator 审中-公开
标题翻译：过程模拟程序，过程模拟方法，过程模拟器
公开(公告)号：JP2010161259A
公开(公告)日：2010-07-22
申请号：JP2009003226
申请日：2009-01-09
申请人： Toshiba Corp , 株式会社東芝
发明人： KUSAKA TOMOMI , KANEMURA TAKANAGA
IPC分类号： H01L21/265 , H01L21/00
CPC分类号： H01L21/2236 , H01J37/32412
摘要： PROBLEM TO BE SOLVED: To provide a process simulation program, a process simulation method, and a process simulator for simply performing simulation for plasma doping treatment with a sufficient accuracy.
SOLUTION: The process simulation program makes a computer execute simulation for a process including the plasma doping treatment. In this simulation, the computer performs processing for associating condition data of plasma doping with condition data for ion implantation where impurities are implanted into a semiconductor as ion beams for conversion, and processing for calculating device structure data based on the condition data for ion implantation obtained through conversion of condition data of plasma doping.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供用于以足够的精度简单地进行等离子体掺杂处理的模拟的过程模拟程序，过程模拟方法和过程模拟器。解决方案：过程仿真程序使计算机执行包括等离子体掺杂处理在内的工艺的仿真。在该模拟中，计算机执行用于将等离子体掺杂的条件数据与用于离子注入的条件数据相关联的处理，其中将杂质注入到半导体中作为离子束进行转换，以及基于用于离子注入的条件数据计算器件结构数据的处理通过转换等离子体掺杂的条件数据。版权所有（C）2010，JPO＆INPIT

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