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1. 发明专利

JP2006121050A Method of causing rram characteristics to be generated by doping into pcmo thin film 审中-公开
标题翻译：通过掺入PCMO薄膜生成的RRAM特性的方法
公开(公告)号：JP2006121050A
公开(公告)日：2006-05-11
申请号：JP2005254723
申请日：2005-09-02
申请人： Sharp Corp , シャープ株式会社
发明人： ZHUANG WEI-WEI , EVANS DAVID R , ZHANG FENGYAN , HSU SHENG TENG
IPC分类号： H01L27/10 , C01G45/00 , H01L43/08
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a doped PCMO layer in a single deposition process.
SOLUTION: The forming method of the doped PCMO thin-film layer which can be applied to RRAM and includes a process that prepares a PCMO precursor solution having a transition metal additive in it, a process that spin-coats a doped PCMO spin coating solution onto a wafer surface and anneals the same after sintered, a process that repeats spin coating several number of times and a process that further performs annealing.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供在单个沉积工艺中形成掺杂的PCMO层的方法。解决方案：可以应用于RRAM的掺杂PCMO薄膜层的形成方法，包括制备其中具有过渡金属添加剂的PCMO前体溶液的方法，旋涂涂布的PCMO旋转将涂布溶液涂覆在晶片表面上，并在烧结后退火，多次重复旋涂的工艺和进一步进行退火的工艺。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006121044A Chemical mechanical polishing of pcmo thin film in rram device 审中-公开
标题翻译： PCMO薄膜在RRAM器件中的化学机械抛光
公开(公告)号：JP2006121044A
公开(公告)日：2006-05-11
申请号：JP2005245555
申请日：2005-08-26
申请人： Sharp Corp , シャープ株式会社
发明人： PAN WEI , EVANS DAVID R , BURMASTER ALLEN
IPC分类号： H01L21/304 , B24B37/00 , H01L27/10
CPC分类号： H01L21/3212 , H01L27/112 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： PROBLEM TO BE SOLVED: To provide a CMR layer of a CMOS integrated circuit by a method that can be commercially achieved in a manufacturing method of the CMR layer in the CMOS integrated circuit, including CMP of the CMR layer in a manufacturing process. SOLUTION: A forming method for forming a CMR layer in a CMOS device, using CMP (chemical mechanical polishing) for patterning the CMR layer comprises a step of preparing a silicon substrate including the formation of a lower electrode in the silicon substrate; a step of depositing an SiN x layer on the silicon substrate; a step of patterning and etching the SiN x layer for forming a damascene trench on the lower electrode; a step of depositing a CMR material layer on the SiN x layer and the damascene trench; a step of removing the CMR material layer, covering the SiN x layer by CMP and leaving the CMR material layer in the damascene trench; and a step of completing a CMOS structure. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过在CMOS集成电路中的CMR层的制造方法中可以商业实现的方法来提供CMOS集成电路的CMR层，包括制造过程中的CMR层的CMP 。解决方案：使用CMP（化学机械抛光）用于在CMR层上构图的在CMOS器件中形成CMR层的形成方法包括制备包括在硅衬底中形成下电极的硅衬底的步骤; 在硅衬底上沉积SiN x 层的步骤; 图案化和蚀刻用于在下电极上形成镶嵌沟槽的SiN 层的步骤; 在SiN x 层和镶嵌沟槽上沉积CMR材料层的步骤; 通过CMP去除CMR材料层，覆盖SiN＆lt; SB＆gt; x＆lt;＆gt;层并留下镶嵌沟槽中的CMR材料层的步骤; 以及完成CMOS结构的步骤。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006080510A METHOD OF FORMING RELAXATION Si1-XGeX (0 审中-公开
标题翻译：通过粘结硼或堇青石形成具有高Ge含量的Si1-XGeX（0
公开(公告)号：JP2006080510A
公开(公告)日：2006-03-23
申请号：JP2005250221
申请日：2005-08-30
申请人： Sharp Corp , シャープ株式会社
发明人： TWEET DOUGLAS J , EVANS DAVID R , HSU SHENG TENG , MAA JER-SHEN
IPC分类号： H01L21/20 , H01L21/265 , H01L29/78
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L29/1054 , Y10S438/933
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a relaxation Si
1-X Ge
X (0 1-X Ge
X (0 1-X Ge
X (0 + ions (18); carrying out annealing to relax the distorted SiGe layer (20), thereby, forming a first relaxation SiGe layer, and completing the semiconductor device.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：待解决的问题：为了提供一种能够降低成本的方法，该方法可以形成一种可以降低成本的松弛Si <1> X X （0 解决方案：根据这种在半导体器件中形成具有高锗含量的缓和Si <1> X （<0 1-X （

4. 发明专利

JP2005203733A Buffered layer memory cell 有权
标题翻译：缓冲层记忆体
公开(公告)号：JP2005203733A
公开(公告)日：2005-07-28
申请号：JP2004259085
申请日：2004-09-06
申请人： Sharp Corp , シャープ株式会社
发明人： TAJIRI MASAYUKI , SHIEN TEN SUU , LI TINGKAI , ZHANG FENGYAN , PAN WEI , ZHUANG WEI-WEI , EVANS DAVID R
IPC分类号： H01L27/10 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： PROBLEM TO BE SOLVED: To provide a method for forming buffered memory cells.
SOLUTION: This method comprises a step for forming a lower electrode 202; a step for forming a colossal magnetoresistance (CMR) memory film 204 arranged on the lower electrode 202, a step for forming a memory-stable semiconductor buffer layer 206 (normally, a metal oxide) arranged on the memory film 204, and a step for forming an upper electrode 208 arranged on the semiconductor buffer layer 206. In some aspects of this method, the semiconductor buffer layer 206 is formed of YBa
2 Cu
3 O
7-X (YBCO), etc., and has a thickness in the range of 10 to 200 nanometers (nm). The upper and lower electrodes 208 and 202 may be TiN/Ti, etc. The CMR memory film 204 may be formed of a Pr
1-X Ca
X MnO
3 (PCMO) memory film, where x is in the region between 0.1 and 0.6 and has a thickness in the range of 10 to 200 nm.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种形成缓冲存储单元的方法。解决方案：该方法包括用于形成下电极202的步骤; 用于形成布置在下电极202上的巨磁阻（CMR）存储膜204的步骤，用于形成布置在存储膜204上的存储稳定半导体缓冲层206（通常为金属氧化物）的步骤，以及用于形成布置在半导体缓冲层206上的上电极208.在该方法的一些方面中，半导体缓冲层206由YBa 2 SB 3 O 3 / 7-X（YBCO）等，并且具有10-200纳米（nm）范围内的厚度。上电极208和下电极202可以是TiN / Ti等.CMR存储器膜204可以由Pr 1-X X SB / 3（PCMO）记忆膜，其中x在0.1至0.6之间的区域中，并且具有在10至200nm范围内的厚度。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004282070A METHOD OF ETCHING SiN/Ir/TaN OR SiN/Ir/Ti STACK USING ALUMINUM HARD MASK 审中-公开
公开(公告)号：JP2004282070A
公开(公告)日：2004-10-07
申请号：JP2004069844
申请日：2004-03-11
申请人： Sharp Corp , シャープ株式会社
发明人： LI TINGKAI , ULRICH BRUCE D , EVANS DAVID R , SHIEN TEN SUU
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/32139 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To provide a highly selective etching technique in an iridium and silicon nitride containing structure.
SOLUTION: A method of etching includes a step of depositing a first etch stop layer 36; a step of forming an iridium lower electrode layer 38; a step of depositing an SiN layer 40; a step of depositing and patterning an aluminum hard mask 42; a step of etching a non-patterned SiN layer 40 with a SiN selective etchant, and a step of stopping at the level of the iridium bottom electrode layer. Further, the method includes a step of etching the first etch stop layer 36 with a second selective etchant; a step of depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; a step of wet etching the SiN layer to form a trench; and a step of depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer.
COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2007067385A Buffer layer forming method for rram thin film deposition 审中-公开
标题翻译：缓冲层形成方法用于RRAM薄膜沉积
公开(公告)号：JP2007067385A
公开(公告)日：2007-03-15
申请号：JP2006210546
申请日：2006-08-02
申请人： Sharp Corp , シャープ株式会社
发明人： ZHUANG WEI-WEI , HSU SHENG TENG , EVANS DAVID R , LI TINGKAI , LAWRENCE J CHARNESKI
IPC分类号： H01L27/10
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： PROBLEM TO BE SOLVED: To provide a forming method of a buffer layer to deposit an RRAM thin film. SOLUTION: The forming method of the buffer layer to deposit the RRAM thin film has a preparing step of preparing a substrate, a lower electrode depositing step of depositing a lower electrode on the above-mentioned substrate, a transition metal film depositing step of depositing the thin film of transition metals having a plurality of valences on the above-mentioned lower electrode, a metal oxide film depositing step of depositing the film of a metal oxide on the above-mentioned transition metal film, an upper electrode deposition step of depositing the upper electrode on the above-mentioned metal oxide film, an annealing step of annealing the plurality of the above-mentioned films formed on the above-mentioned substrate and the above-mentioned substrate, and an RRAM forming step of completing the RRAM. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供缓冲层的形成方法以沉积RRAM薄膜。解决方案：沉积RRAM薄膜的缓冲层的形成方法具有准备基板的准备步骤，在上述基板上沉积下电极的下电极沉积步骤，过渡金属膜沉积步骤在上述下部电极上沉积具有多个价态的过渡金属的薄膜的金属氧化物膜沉积步骤，在上述过渡金属膜上沉积金属氧化物的膜;上部电极淀积步骤，在上述金属氧化物膜上沉积上电极，对形成在上述基板上的多个上述膜和上述基板进行退火的退火步骤以及完成RRAM的RRAM形成步骤。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006121068A Selective etching treatment method for thin films of sio2, ti and in2o3 applied to feram device 审中-公开
标题翻译：适用于FERAM器件的SIO2，TI和In2O3薄膜选择性蚀刻处理方法
公开(公告)号：JP2006121068A
公开(公告)日：2006-05-11
申请号：JP2005290587
申请日：2005-10-03
申请人： Sharp Corp , シャープ株式会社
发明人： LI TINGKAI , ULRICH BRUCE D , EVANS DAVID R , SHIEN TEN SUU
IPC分类号： H01L21/3065 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： H01L29/6684 , C23F4/00 , H01L21/28291 , H01L21/31116 , H01L21/32136
摘要： PROBLEM TO BE SOLVED: To provide a selective etching technology for the thin films of SiO
2 , titanium and In
2 O
3 used for MFMox.
SOLUTION: The method that selectively etches the thin-film three-layer structure, includes an etching of SiO
2 that is stopped in a titanium layer that uses C
3 F
8 within a scope of about 10 to 30 sccms and argon within the range of about 20 to 40 sccms, and RF source within the range of about 1,000 to 3,000 watts and RF bias within a range of about 400 to 800 watts under a pressure within the range of about 2 to 6 mtorrs, and etching of titanium that is stopped in an In
2 O
3 layer that uses BCl within the range of about 10 to 50 sccms, Cl within the range of about 40 to 80 sccms, and Tcp within the range of about 200 to 500 watts under pressure within the range of about 4 to 8 mtorrs and RF bias within the range of about 100 to 200 watts.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供用于SiO 2 SBI薄膜的钛和In使用的选择性蚀刻技术对于MFMox。＆lt; P＆gt;解决方案：选择性地蚀刻薄膜三层结构的方法包括在使用C 3 SB 3的Ti层中停止的SiO 2 在约10至30sccms范围内的氩气和约20至40sccms范围内的氩气，以及在约1,000至3,000瓦特范围内的RF源和在约在约2至6m范围内的压力下400至800瓦特，以及在使用BCl的InCl 2层中停止的钛的蚀刻约10至50sccms的范围，Cl在约40至80sccms的范围内，Tcp在约200至500瓦特的范围内，在约4至8m范围内的压力下，RF偏压在约100范围内至200瓦。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006024901A Surface treatment method of substrate for depositing rram thin film 审中-公开
标题翻译：用于沉积RRAM薄膜的衬底的表面处理方法
公开(公告)号：JP2006024901A
公开(公告)日：2006-01-26
申请号：JP2005153276
申请日：2005-05-26
申请人： Sharp Corp , シャープ株式会社
发明人： ZHUANG WEI-WEI , LI TINGKAI , PAN WEI , EVANS DAVID R , HSU SHENG TENG
IPC分类号： H01L27/105 , B28B1/30 , C23C18/12 , C30B23/02 , C30B29/24 , H01F10/18 , H01F10/32 , H01F41/24 , H01L21/44 , H01L21/8246 , H01L43/08 , H01L43/12 , H01L45/00
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1241 , C23C18/1283 , C30B23/02 , C30B29/24 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： PROBLEM TO BE SOLVED: To provide a programmable CMR thin film by using spin coating processing.
SOLUTION: This method process includes a step 10 of preparing a CMR precursor comprising metal-acetate-base acetum; a step of preparing a wafer; a step of setting the wafer in a spin coating chamber; a step of performing spin coating and heating to the wafer which is repeated at least three times; a step 26 of performing post annealing to the wafer for about 1 to 6 hours at a temperature range of about 500 to 600°C in dry and clean air; and a step of forming a semiconductor device. The step of performing spin coating and heating includes a step 14 of injecting the CMR precursor into the surface of the wafer in the chamber; a step 16 of accelerating the wafer to a spin speed of about 1,500 to 3,000 rpm for about 30 seconds; a step 18 of baking the wafer at about 180°C for about 1 min; a step 20 of heating the wafer to about 230°C and then baking the wafer for about 1 min; and a step 22 of annealing the wafer at about 500°C for about 5 min.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过旋涂处理提供可编程CMR薄膜。解决方案：该方法方法包括制备包含金属 - 乙酸酯 - 基乙缩醛的CMR前体的步骤10; 准备晶片的步骤; 将晶片设置在旋涂室中的步骤; 对晶片进行旋涂和加热至少三次的步骤; 在干燥和清洁的空气中在约500-600℃的温度范围内对晶片进行约1至6小时的后退火的步骤26; 以及形成半导体器件的步骤。进行旋涂和加热的步骤包括将CMR前体注入室中的晶片表面的步骤14; 将晶片加速至约1500至3000rpm的旋转速度约30秒的步骤16; 在约180℃下烘烤晶片约1分钟的步骤18; 将晶片加热到约230℃，然后将晶片烘烤约1分钟的步骤20; 以及在约500℃退火晶片约5分钟的步骤22。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2006005351A Method for forming metal pattern by plating method 审中-公开
标题翻译：通过镀层法形成金属图案的方法
公开(公告)号：JP2006005351A
公开(公告)日：2006-01-05
申请号：JP2005173051
申请日：2005-06-13
申请人： Sharp Corp , シャープ株式会社
发明人： EVANS DAVID R , HARTZELL JOHN W
IPC分类号： H01L21/288 , C23C18/16 , C23C18/54 , C25D1/04 , C25D5/02 , C25D5/54 , G02F1/13 , G02F1/1343 , G02F1/1345 , H01L21/28 , H01L21/768
CPC分类号： H01L21/288 , C23C18/1605 , C23C18/165 , C23C18/1657 , C25D1/003 , C25D5/022 , C25D5/50 , H01L21/2885 , H01L21/76885
摘要： PROBLEM TO BE SOLVED: To provide a method for suitably electrocasting a metal integrated circuit structure.
SOLUTION: The surface (104) of a substrate (102) is exposed by forming an opening (108), such as a via or a line penetrating an intermediate insulator; a base layer (110) on the intermediate insulator (106) and the surface of the substrate is formed; a strike layer (112) on the base layer is formed, an uppermost layer on the strike layer is formed, and the surface of the strike layer (112) is exposed by performing selective etching, to remove the uppermost layer on the surface of the substrate; and thus a metal structure (114) on the surface of the strike layer is electrocast. The electrocast metal structure (114) is deposited, using electric plating or non-electrolytic deposition process. Typically, this metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于适当地电铸金属集成电路结构的方法。解决方案：通过形成诸如通过中间绝缘体的通孔或线的开口（108）来暴露基板（102）的表面（104）形成在中间绝缘体（106）上的基底层（110）和基板的表面; 形成在基底层上的冲击层（112），在冲击层上形成最上层，通过进行选择性蚀刻使冲击层（112）的表面露出，从而去除表面上的最上层基质; 因此在冲击层的表面上的金属结构（114）是电铸的。使用电镀或非电解沉积工艺沉积电铸金属结构（114）。通常，该金属是Cu，Au，Ir，Ru，Rh，Pd，Os，Pt或Ag。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2004197227A Source alternate mocvd process of depositing tungsten nitride thin film as barrier layer for mocvd copper interconnection 审中-公开
标题翻译：用于MOCVD铜互连的沉积硝酸盐薄膜作为阻挡层的源替代MOCVD工艺
公开(公告)号：JP2004197227A
公开(公告)日：2004-07-15
申请号：JP2003421943
申请日：2003-12-19
申请人： Sharp Corp , シャープ株式会社
发明人： PAN WEI , EVANS DAVID R , SHIEN TEN SUU
IPC分类号： C23C16/34 , H01L21/285 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/28556 , H01L2221/1078
摘要： PROBLEM TO BE SOLVED: To form a WN barrier layer having high density, low resistivity, and extremely fine crystal grains or an amorphous structure.
SOLUTION: The process is a source alternate CVD (Chemical Vapor Deposition) process for forming a WN barrier layer, and includes: a stage (a) where a substrate is heated inside a CVD chamber; a stage (b) where an alternate source W(CO)
6 precursor is introduced into the CVD chamber; and a stage (c) where an NH
3 source is introduced into the chamber. The process further includes a stage where the W(CO)
6 and NH
3 are reacted, and WN is deposited on the heated substrate.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：形成具有高密度，低电阻率和极细晶粒或无定形结构的WN阻挡层。解决方案：该方法是用于形成WN阻挡层的源替代CVD（化学气相沉积）方法，并且包括：在CVD室内加热基板的载物台（a）将备用源W（CO）SB 6前体引入CVD室的阶段（b）; 以及将NH 3 SB 3源引入室中的阶段（c）。该方法还包括使W（CO）SB 6和NH 3 SB 3反应的阶段，并且WN沉积在加热的基底上。版权所有（C）2004，JPO＆NCIPI

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