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1. 发明专利

JP2005340786A Formation method of pcmo thin film having memory resistance property and pcmo device 审中-公开
标题翻译：具有存储电阻性能的PCMO薄膜的形成方法和PCMO器件
公开(公告)号：JP2005340786A
公开(公告)日：2005-12-08
申请号：JP2005123111
申请日：2005-04-21
申请人： Sharp Corp , シャープ株式会社
发明人： ZHUANG WEI-WEI , LI TINGKAI , HSU SHENG TENG , ZHANG FENGYAN
IPC分类号： H01L27/105 , H01L21/00 , H01L21/20 , H01L27/10 , H01L45/00 , H01L49/02
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： PROBLEM TO BE SOLVED: To provide a PCMO device having a reversible resistance switch property according to a unipolar or bipolar voltage pulse, and a formation method of a PCMO thin film.
SOLUTION: In a formation method of a PCMO (Pr
0.3 Ca
0.7 MnO
3 ) thin film having a crystal state associated with a memory resistance property, a step of forming a PCMO thin film having a first crystal state, and a step of changing a resistance condition of the PCMO thin film by using pulse polarity according to the first crystal state.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供根据单极或双极电压脉冲具有可逆电阻开关特性的PCMO器件和PCMO薄膜的形成方法。＆lt; P＆gt;解决方案：在具有与a相关的晶体状态的PCMO（Pr 0.3 > MnO 3 SB 3）的形成方法中，记忆电阻性，形成具有第一晶体状态的PCMO薄膜的步骤，以及通过使用根据第一晶体状态的脉冲极性来改变PCMO薄膜的电阻状态的步骤。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2003023139A Single c-axis pgo thin film electrode with superior smooth surface and uniformity and its forming method 审中-公开
标题翻译：具有超级平滑表面和均匀性的单C轴PGO薄膜电极及其形成方法
公开(公告)号：JP2003023139A
公开(公告)日：2003-01-24
申请号：JP2002081747
申请日：2002-03-22
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , MAA JER-SHEN , ZHUANG WEI WEI , SHIEN TEN SUU
IPC分类号： C23C14/08 , C23C16/40 , H01L21/02 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
CPC分类号： H01L28/56 , C23C16/40 , H01L21/31691 , H01L28/55 , H01L28/60 , H01L28/75 , Y10T428/24917 , Y10T428/2495
摘要： PROBLEM TO BE SOLVED: To provide a (c) axis orientation single crystal PGO ferroelectric thin film whose thickness is uniform on a metal electrode. SOLUTION: This forming method is a method for forming an electrode and the ferroelectric thin film on the electrode, and consists of a process for forming a substrate and a process for depositing the electrode on the substrate. The electrode is formed of material obtained from material group composed of iridium and iridium composite. A process for forming the ferroelectric thin film includes a process wherein the film shows the smooth surface and uniform thickness.
摘要翻译：要解决的问题：提供在金属电极上厚度均匀的（c）轴向取向单晶PGO铁电薄膜。解决方案：该形成方法是在电极上形成电极和铁电薄膜的方法，并且由用于形成基板的工艺和在基板上沉积电极的工艺组成。电极由由铱和铱复合材料组成的材料组成。形成铁电薄膜的方法包括其中所述膜显示光滑表面和均匀厚度的方法。

3. 发明专利

JP2002367929A Iridium containing high thermal stability nickel silicide used for ultrathin junction formation part, and its manufacturing method 有权
标题翻译：含有高温稳定性的镍镉镍硅胶用于超导结形成部分及其制造方法
公开(公告)号：JP2002367929A
公开(公告)日：2002-12-20
申请号：JP2002127643
申请日：2002-04-26
申请人： Sharp Corp , シャープ株式会社
发明人： MAA JER-SHEN , YOSHI ONO , ZHANG FENGYAN
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336
CPC分类号： H01L21/28518
摘要： PROBLEM TO BE SOLVED: To preserve integrity and stability of the junction part of a silicide layer even at a temperature of 800°C or over.
SOLUTION: These are an integrated circuit device which is equipped with a nickel silicide made together with an iridium middle layer on a silicon substrate, and its manufacturing method. The above method includes a process of depositing an iridium(Ir) interface layer between an Ni layer and an Si layer before execution of reaction for silicification. The thermal stability of the nickel silicide rises remarkably by adding the thin iridium layer. Even if the annealing temperature is 850°C, the low junction leakage current at an ultrathin junction formation part is materialized by the low sheet resistance of the silicide.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了保持硅化物层的接合部分的完整性和稳定性，甚至在800℃或更高的温度下。解决方案：这些是在硅衬底上配备有与铱中间层一起制造的硅化镍的集成电路器件及其制造方法。上述方法包括在执行硅化反应之前在Ni层和Si层之间沉积铱（Ir）界面层的工艺。通过添加薄铱层，硅化镍的热稳定性显着上升。即使退火温度为850℃，通过硅化物的薄片电阻也能够实现超薄结形成部的低结漏电流。

4. 发明专利

JP2007281457A Variable resistive element and its forming method 审中-公开
标题翻译：可变电阻元件及其形成方法
公开(公告)号：JP2007281457A
公开(公告)日：2007-10-25
申请号：JP2007084679
申请日：2007-03-28
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , MAA JER SHEN , PAN WEI , HSU SHENG TENG
IPC分类号： H01L49/00 , H01L27/10 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To provide a variable resistive element equipped with a low resistance PCMO (Pr 0.7 Ca 0.3 MnO 3 ) film having an excellent rewriting resistance value and capable of realizing bipolar electrical pulse switching characteristics. SOLUTION: The forming method of the variable resistive element comprises a preparation process for preparing a silicon substrate, a first process for depositing a lower electrode on the silicon substrate, a second process for depositing a thin film containing PCMO-platinum with PCMO as well as platinum mixed therein, and a third process for depositing an upper electrode on the thin film containing PCMO-platinum. Preferably in the second process, the thin film containing PCMO-platinum is formed as a multi-layered structure film by depositing the PCMO film and the platinum film alternately, or the thin film containing PCMO-platinum is formed through the co-deposit of PCMO and platinum. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种配备低电阻PCMO（Pr 0.7 Ca 0.3 MnO 3 ）膜的可变电阻元件具有优异的重写电阻值并且能够实现双极电脉冲开关特性。解决方案：可变电阻元件的形成方法包括制备硅衬底的制备方法，用于在硅衬底上沉积下电极的第一工艺，用PCMO沉积含有PCMO-铂的薄膜的第二工艺以及混入其中的铂，以及在含有PCMO-铂的薄膜上沉积上电极的第三工艺。优选地，在第二工序中，通过交替地沉积PCMO膜和铂膜，形成含有PCMO-铂的薄膜作为多层结构膜，或者通过PCMO的共沉积形成含有PCMO-铂的薄膜和铂金。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006203178A Nonvolatile memory resistor cell and its manufacturing method 有权
标题翻译：非易失性存储器电阻器及其制造方法
公开(公告)号：JP2006203178A
公开(公告)日：2006-08-03
申请号：JP2005361983
申请日：2005-12-15
申请人： Sharp Corp , シャープ株式会社
发明人： HSU SHENG TENG , ZHANG FENGYAN , STECKER GREGORY M , BARROWCLIFF ROBERT A
IPC分类号： H01L27/10 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory resistor cell of an asymmetric structure which can be rewritten by bipolar pulse and its manufacturing method.
SOLUTION: The manufacturing method includes formation of a first electrode 102 with a nano-chip 104, formation of a memory resistor material 106 adjacent to the nano-chip 104, and formation of a second electrode 108 adjacent to the memory resistor material 106, so in the result, the memory resistor material 106 is put between the first electrode 102 and the second electrode 108. Usually, the nano-chip 104 is made of iridium oxide (IrO
x ) of which bottom size is about 50 nm or less, projection height is within 5 to 50 nm and projection density is more than 100 per 1μm
2 . In an embodiment, material of a substrate is selected from among silicon, silicon oxide, silicon nitride, and noble metal. Metal-organic chemical vapor deposition (MOCVD) is used to deposit Ir and IrO
x nano-chip grows from the deposited Ir.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以通过双极脉冲重写的非对称结构的非易失性存储器电阻单元及其制造方法。解决方案：制造方法包括用纳米芯片104形成第一电极102，形成与纳米芯片104相邻的存储电阻材料106，以及形成与存储电阻材料相邻的第二电极108 因此，结果，存储电阻材料106被放置在第一电极102和第二电极108之间。通常，纳米芯片104由其中的氧化铱（IrO SB SB）x 底部尺寸为约50nm或更小，突出高度在5至50nm内，并且投影密度大于100 /1μm 2 。在一个实施例中，衬底的材料选自硅，氧化硅，氮化硅和贵金属。金属有机化学气相沉积（MOCVD）用于沉积Ir和IrO x 纳米芯片从沉积的Ir生长。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006060202A IRIDIUM ETCHING FOR USE IN FeRAM 审中-公开
标题翻译：用于FeRAM的IRIDIUM蚀刻
公开(公告)号：JP2006060202A
公开(公告)日：2006-03-02
申请号：JP2005215145
申请日：2005-07-25
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , EVANS DAVID R , PAN WEI , STECKER LISA H , MAA JER-SHEN
IPC分类号： H01L21/3065 , H01L21/3213 , H01L21/8246 , H01L27/105
CPC分类号： H01L21/32136 , H01L21/28291
摘要： PROBLEM TO BE SOLVED: To provide an iridium etching process for use in FeRAM exhibiting high selectivity to a hard mask and a lower layer.
SOLUTION: The etching method (10) of an iridium layer for use in a ferroelectric device comprises a step for preparing a substrate (12), a step for depositing a barrier layer (14) on the substrate, a step for depositing the iridium layer on the barrier layer (16), a step for depositing a hard mask layer on the iridium layer (18), a step for depositing a photoresist layer on the hard mask layer and then patterning and depositing it (20), a step for etching the hard mask layer (22), a step for etching the iridium layer in a high density plasma reaction furnace by using argon, oxygen and chlorine components (24), and a step for completing the ferroelectric device (26).
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于对硬掩模和下层具有高选择性的FeRAM的铱蚀刻工艺。解决方案：用于铁电体器件的铱层的蚀刻方法（10）包括制备衬底（12）的步骤，用于在衬底上沉积阻挡层（14）的步骤，用于沉积阻挡层（16）上的铱层，用于在铱层（18）上沉积硬掩模层的步骤，用于在硬掩模层上沉积光致抗蚀剂层然后图案化和沉积它的步骤（20），用于蚀刻硬掩模层（22）的步骤，通过使用氩，氧和氯组分（24）在高密度等离子体反应炉中蚀刻铱层的步骤和用于完成铁电体器件（26）的步骤。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003273333A Polycrystalline memory structure and its manufacturing method, and semiconductor memory device using it 审中-公开
标题翻译：多晶体存储器结构及其制造方法和使用它的半导体存储器件
公开(公告)号：JP2003273333A
公开(公告)日：2003-09-26
申请号：JP2002360043
申请日：2002-12-11
申请人： Sharp Corp , シャープ株式会社
发明人： SHIEN TEN SUU , LI TINGKAI , ZHANG FENGYAN , ZHUANG WEI-WEI
IPC分类号： H01L27/10 , H01L21/02 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L43/08 , H01L45/00
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： PROBLEM TO BE SOLVED: To improve reliability and yield of a device by restraining a leakage current of a polycrystalline memory thin film used in a memory cell.
SOLUTION: A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within gaps to at least partially block entrance to the gaps. A method for forming a polycrystalline memory structure is also described. A material layer is deposited and annealed to form a polycrystalline memory material having the gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过抑制存储单元中使用的多晶硅存储薄膜的漏电流来提高器件的可靠性和产量。解决方案：描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层，所述多晶存储器层具有在衬底上相邻微晶之间形成间隙的晶粒边界。绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。还描述了一种用于形成多晶存储器结构的方法。材料层被沉积并退火以形成具有相邻微晶间隙的多晶记忆材料。绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。版权所有（C）2003，JPO

8. 发明专利

JP2006060203A Pt/PGO ETCHING PROCESS FOR USE IN FeRAM 审中-公开
标题翻译： Pt / PGO蚀刻过程用于FeRAM
公开(公告)号：JP2006060203A
公开(公告)日：2006-03-02
申请号：JP2005215151
申请日：2005-07-25
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , ULRICH BRUCE D , STECKER LISA H , SHIEN TEN SUU
IPC分类号： H01L21/3065 , H01L21/8246 , H01L27/105
CPC分类号： H01L21/32139 , H01L21/32136 , H01L27/1085 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To provide an etching process for minimizing the damage of etching on a ferroelectric layer.
SOLUTION: The method for etching a noble metal upper electrode on a ferroelectric layer while sustaining ferroelectric characteristics thereof and removing etching residues comprises a step (14) for depositing a barrier layer on a prepared substrate, a step (18) for depositing a ferroelectric layer on a lower electrode layer deposited on the barrier layer, a step (22) for depositing an adhesive layer on an upper electrode layer deposited on the ferroelectric layer, a step (28) for patterning a hard mask deposited on the adhesive layer, a step (30) for etching the noble metal upper electrode layer by predetermined substrate RF bias power producing etching residues in the first etching process, and a step (32) for removing the etching residues in the first etching process by overetching the noble metal upper electrode layer and the ferroelectric layer by RF bias power lower than the predetermined RF bias power.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于最小化铁电层上的蚀刻损伤的蚀刻工艺。解决方案：在维持其铁电特性并去除蚀刻残留物的同时在铁电体层上蚀刻贵金属上电极的方法包括用于在制备的基板上沉积阻挡层的步骤（14），用于沉积步骤沉积在阻挡层上的下电极层上的铁电层，沉积在强电介质层上的上电极层上沉积粘合剂层的步骤（22），用于将沉积在粘合剂层上的硬掩模图形化的步骤，用于通过在第一蚀刻工艺中产生蚀刻残留物的预定衬底RF偏置功率蚀刻贵金属上电极层的步骤（30），以及用于通过过蚀化贵金属来去除第一蚀刻工艺中的蚀刻残留物的步骤（32）上电极层和铁电层通过低于预定的RF偏压功率的RF偏置功率。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005064502A High-temperature annealing of spin-coated pr1-xcaxmno3 thin film for rram application 有权
标题翻译：用于RRAM应用的旋涂PR1-XCAXMNO3薄膜的高温退火
公开(公告)号：JP2005064502A
公开(公告)日：2005-03-10
申请号：JP2004229953
申请日：2004-08-05
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , ZHUANG WEI-WEI , EVANS DAVID R , SHIEN TEN SUU
IPC分类号： H01L21/28 , G11C13/00 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/10 , H01L27/115 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： PROBLEM TO BE SOLVED: To form a PCMO thin-film having bipolar electric-pulse switching characteristics used for a RRAM application. SOLUTION: The method for forming a PCMO thin-film in a RRAM device includes: forming a lower electrode on a metal barrier layer on a substrate; spin-coating a Pr 1-x Ca x MnO 3 layer on the lower electrode, using a PCMO precursor; baking the PCMO thin-film in at least one baking step; annealing the PCMO thin-film in a first annealing step, after each spin-coating step; performing the spin-coating step, baking step, and first annealing step repeatedly to obtain the desired thickness of the PCMO thin-film; and annealing the PCMO thin-film in a second annealing step, thereby generating a PCMO thin-film having a crystal structure of Pr 1-X Ca X MnO 3 , where X is such that 0.2≤X≤0.5. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：形成具有用于RRAM应用的双极电脉冲开关特性的PCMO薄膜。解决方案：在RRAM器件中形成PCMO薄膜的方法包括：在衬底上的金属阻挡层上形成下电极; 使用PCMO前体在下电极上旋涂Pr 1-x Ca MnO 3 SBS 3 层; 在至少一个烘烤步骤中烘烤PCMO薄膜; 在每个旋涂步骤之后，在第一退火步骤中退火PCMO薄膜; 进行旋涂步骤，烘烤步骤和第一退火步骤以获得所需的PCMO薄膜厚度; 并在第二退火步骤中对PCMO薄膜进行退火，从而产生具有Pr 1-X X MnO 3的晶体结构的PCMO薄膜，其中X为0.2≤X≤0.5。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004311969A Method for fabricating nano-scale resistance cross-point memory array and device 有权
公开(公告)号：JP2004311969A
公开(公告)日：2004-11-04
申请号：JP2004071736
申请日：2004-03-12
申请人： Sharp Corp , シャープ株式会社
发明人： SHIEN TEN SUU , ZHUANG WEI-WEI , PAN WEI , ZHANG FENGYAN
IPC分类号： H01L27/105 , G11C13/00 , H01L21/8246 , H01L27/115 , H01L27/24 , H01L43/08
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： PROBLEM TO BE SOLVED: To provide a method for fabricating a nano-scale resistance cross-point memory array which incorporates a ferroelectric ultra giant magnetic resistance based resistor having lower power consumption, lower programming current and higher capability of being integrated in high density than the other memories.
SOLUTION: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array.
COPYRIGHT: (C)2005,JPO&NCIPI

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