专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2005322068A Memory interface integration system 审中-公开
标题翻译：记忆界面整合系统
公开(公告)号：JP2005322068A
公开(公告)日：2005-11-17
申请号：JP2004140200
申请日：2004-05-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOYOKURA MAKI
IPC分类号： G06F13/16 , G06F1/06 , G06F15/78 , H04J3/00
摘要： PROBLEM TO BE SOLVED: To provide an SoC (System on Silicon) reducing correction of a memory interface of an LSI core, and capable of easily integrating the LSI core without changing an access method of each the LSI core. SOLUTION: An SoC side and a memory side each have a multiplex circuit for a transmission signal, and a separation circuit for a reception signal. The transmission signal of the memory interface of each the LSI core is time-multiplexed and is transmitted to the memory side, and is time-separated on the memory side and is transmitted to each SDRAM core. The transmission signal of each the SDRAM core is time-multiplexed and is transmitted to the SoC side, and is time-separated on the SoC side and is transmitted to each the LSI core. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种减少LSI核的存储器接口的校正的SoC（硅上系统），并且能够容易地集成LSI核，而不改变每个LSI核的访问方法。解决方案：SoC侧和存储器侧各自具有用于发送信号的多路复用电路和用于接收信号的分离电路。每个LSI核的存储器接口的发送信号被时分多路复用，并被发送到存储器侧，并且在存储器侧被时间分隔并被发送到每个SDRAM内核。每个SDRAM内核的发送信号被时分多路复用，并传输到SoC侧，并在SoC侧进行时间分离，并发送给每个LSI内核。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2004287576A Bus controller 审中-公开
公开(公告)号：JP2004287576A
公开(公告)日：2004-10-14
申请号：JP2003076055
申请日：2003-03-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOYOKURA MAKI
IPC分类号： G06F13/362 , G06F12/00 , G06F13/16 , G06F13/18
CPC分类号： G06F13/1605
摘要： PROBLEM TO BE SOLVED: To provide a bus controller for suppressing the increase of costs due to a bus system design with a high frequency corresponding to the maximum number of cycles which is less frequent, and for designing the bus system with the number of cycles smaller than the maximum number of cycles, that is, a low frequency for suppressing the re-design of the bus system even when the maximum number of cycles is increased.
SOLUTION: Requesters 23, 24 or 63, 64, and 65 for making access requests to a shared memory 21 are provided with processing means in processing levels whose number of cycles is different respectively, and when it is predicted that the number of cycles exceeds the limited number of cycles on the basis of the current number of cycles, the processing level whose number of cycles is small is selected. Alternatively, the bus access request in a non-real time system is controlled so as not to be permitted, and the bus system is designed with the number of cycles smaller than the total sum of the maximum number of access cycles of all the requesters and the maximum number of times of access.
COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JPH09305397A EXTERNAL CONTROL METHOD FOR MICROCOMPUTER 失效
公开(公告)号：JPH09305397A
公开(公告)日：1997-11-28
申请号：JP12543096
申请日：1996-05-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIMORI TOSHIMASA , TOYOKURA MAKI
IPC分类号： G06F9/26
摘要： PROBLEM TO BE SOLVED: To perform operation change control from the outside while maintaining a high-speed operation by activating instruction analysis change signals from the outside for a control instruction and changing the setting of an instruction analysis part. SOLUTION: A part whose role is changed by setting change from the outside is prepared in the bit field of the control instruction and control is changed by using the instruction analysis part 63 capable of analyzing the change of the role of the control instruction. That is, the instruction analysis part 63 analyzes control contents and a branching instruction is analyzed. Thus, the branching instruction is inserted by the control from the outside, the control contents written in a control memory 61 are changed and the external control of a microcomputer is made possible. Thus, by activating the instruction analysis change signals 65 and changing the setting of the instruction analysis part 63, the increase of additional circuits is suppressed and the external control of the microcomputer is performed without damaging a high speed property.

4. 发明专利

JPH09246978A QUANTIZATION/INVERSE QUANTIZATION CIRCUIT 失效
公开(公告)号：JPH09246978A
公开(公告)日：1997-09-19
申请号：JP4575996
申请日：1996-03-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OKAMOTO KIYOSHI , ARAKI TOSHIYUKI , TOYOKURA MAKI
IPC分类号： G11B20/14 , H03H17/02 , H03M7/02
摘要： PROBLEM TO BE SOLVED: To reduce a scale, to perform acceleration and to lower power consumption by performing the first multiplication between a quantization weight coefficient and a quantization step size by a multiplier and the second multiplication between the result and an inverse quantization level for plural inverse quantization levels. SOLUTION: The quantization weight coefficient 105 is read from a first memory 101 in a memory read means(MR) 103 and an inverse quantization value level 106 (Qij) is read from a second memory 102 in the MR 104. One coefficient is read for every six cycles for the coefficient 105 and one coefficient is read for each cycle in a zigzag order to the picture elements 0,..., 63 of blocks 0-5 for the inverse quantization value level 106. The quantization step size 107 is fixed to mq for a processing period for one macroblock. The quantization weight coefficient Q0.0 is inputted to a first selector(SC) 112, the mq is inputted to a second SC 113, they are multiplied in the multiplier 114 and plural inverse quantization values 118 are outputted from an offset computing element 117.

5. 发明专利

JP2574563B2 失效
公开(公告)号：JP2574563B2
公开(公告)日：1997-01-22
申请号：JP21692391
申请日：1991-08-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KODAMA HISASHI , AONO KUNITOSHI , TOYOKURA MAKI , ARAKI TOSHUKI , OOTANI AKIHIKO , OKAMOTO KYOSHI
IPC分类号： G06T5/20

6. 发明专利

JPH07114432A PRECHARGE DEVICE 失效
公开(公告)号：JPH07114432A
公开(公告)日：1995-05-02
申请号：JP26076193
申请日：1993-10-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYAKE JIRO , NINOMIYA KAZUKI , TOYOKURA MAKI , UCHIUMI NORIO , GION MASAHIRO
IPC分类号： G11C11/41 , G06F3/00
摘要： PURPOSE:To reduce power consumption by detecting a threshold level of transistors (TRs) to terminate precharging thereby decreasing a precharge potential to a signal line and decreasing a time required for pre-charging and an output time of a signal to the signal line. CONSTITUTION:This device is provided with a detection circuit 2 comprising a P-channel MOS TR 7 and N-channel MOS TRs 4, 5 connected in series and a precharge control circuit 3 comprising a P-channel MOS TR 10, a NAND circuit 8 and a delay circuit 11. And a control signal is given to gates of the TRs 7, 4 and the control circuit 11, the output of the delay circuit 11 and a signal line 6 detecting a threshold level VT with the TR 5 whose gate connects to a signal line l9, is inputted to the NAND circuit 8, its output is given to a gate of the TR 10 to control precharging of the signal line 19.

7. 发明专利

JPH06161714A MULTIPLYING AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH06161714A
公开(公告)日：1994-06-10
申请号：JP31473692
申请日：1992-11-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MINEMARU TAKAYUKI , TOYOKURA MAKI
IPC分类号： G06F7/52 , G06F7/533
摘要： PURPOSE:To provide the multiplying and dividing circuit capable of performing both multiplication and division with a single circuit. CONSTITUTION:The multiplying and dividing circuit, constituted by adding a means which sets the input 8 of a dividend to a cell array 3 to '0' and a means which adds a divisor by an addition means corresponding to the digit of the dividend '1' to a cell array type dividing circuit formed by cascading plural addition means, is used to perform division and multiplication. The multiplying and dividing circuit codes a multiplier according to secondary Booth algorithm, generates partial products according to the coded signal, and adds the partial products by the stages corresponding to the code digits to perform multiplication. Further, a function which performs the multiplication changes the direction of a flow of the arithmetic in the cell array 3 from the stage of the low digit position to the stage of the high digit position reversely to the division is added.

8. 发明专利

JPH0561901A PROGRAM CONTROL TYPE PROCESSOR 失效
公开(公告)号：JPH0561901A
公开(公告)日：1993-03-12
申请号：JP21834191
申请日：1991-08-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： AONO KUNITOSHI , TOYOKURA MAKI , ARAKI TOSHIYUKI , OTANI AKIHIKO , KODAMA HISASHI , OKAMOTO KIYOSHI
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F17/10 , G06F17/16
摘要： PURPOSE:To obtain a program control type processor which can attain the high performance by using with control a pipeline computing element as the resources of a general-purpose processor of a program control system. CONSTITUTION:A program control circuit 1 stops the working of an internal program counter and repeats the executing cycle of a vector pipeline instruction. An address generator 2 produces continuously (m) pieces of addresses in the prescribed sequence end with a start signal received from the circuit 1 and then reads continuously (m) pieces of memories out of a data memory 13 to start the executing cycle. At the same time, the circuit 1 controls the function of a data processing circuit 4 and a pipeline constitution. The generator 2 gives an end signal to the circuit 1 when the generation of (m) pieces of addresses is complete. The circuit 1 receives the end signal and then restarts the program counter with delay of two cycles. Then the instructions following a specific one of an address N are carried out in sequence.

9. 发明专利

JPH04147376A VECTOR OPERATION CIRCUIT 失效
公开(公告)号：JPH04147376A
公开(公告)日：1992-05-20
申请号：JP27173790
申请日：1990-10-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OKAMOTO KIYOSHI , AONO KUNITOSHI , TOYOKURA MAKI , ARAKI TOSHIYUKI , OTANI AKIHIKO , KODAMA HISASHI
IPC分类号： H03H17/02 , G06F17/16
摘要： PURPOSE:To enable a vector operation circuit to be available for various applications by providing a vector operation circuit with a bit accuracy variable function for the vector operation. CONSTITUTION:Initial value setting circuit 1 sets the N-th bit counting from the lowest bit position of an initial value at '1', or carries out the action equivalent to adding '1' resulting from subtraction of two complements of F(A(k), b(k, n)) with n=0 to the initial value, and the position of the half-adjusted bit in response to bit accuracy is set at '1', while other bits are all set at '0'. Furthermore, a bit accuracy input is prepared to realize a variable function for the position of a half-adjusting bit in response to bit accuracy. With this, the present vector operation circuit is available for various applications that requires vector operation for various bit accuracy, thereby being able to obtain very useful effect.

10. 发明专利

JPH04114233A DATA ORDER CHANGE CIRCUIT 失效
公开(公告)号：JPH04114233A
公开(公告)日：1992-04-15
申请号：JP23487690
申请日：1990-09-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TOYOKURA MAKI , AONO KUNITOSHI , ARAKI TOSHIYUKI , OTANI AKIHIKO , KODAMA HISASHI , OKAMOTO KIYOSHI
IPC分类号： G06F7/24 , G06T9/00 , H04N1/419 , H04N7/24 , H04N19/00 , H04N19/423 , H04N19/436 , H04N19/60 , H04N19/625 , H04N19/91
摘要： PURPOSE:To rearrange data with the small number of cycles by writing the output data of a RAM for table in a pipe-line register, reading out data from a RAM for input with this data as an address, temporarily fetching this data into the pipe-line register and afterwards writing it into a memory for output. CONSTITUTION:A data is read out from a RAM 11 for table with an address generated by a first address generation circuit 16, and this data is written in a first pipe-line register 14. With the data of the pipe-line register 14 as an address, the data of a RAM 12 for input is read out and this data is written in a pipe-line register 14. In respect to a RAM 13 for output, the data of a second pipe-line register 15 is written in an address generated by a second address generation circuit 17. In this way, the data of the RAM 12 for input is written in the RAM 13 for output while changing the order of the data according to the contents of the RAM 11 for table. Thus, the order of the data can be changed with the almost 1/3 number of cycles in comparison with the conventional data order change circuit.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式