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1. 发明专利

JPH07221625A BUFFER CIRCUIT 失效
公开(公告)号：JPH07221625A
公开(公告)日：1995-08-18
申请号：JP1450294
申请日：1994-02-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TOYOKURA MAKI , MIYAKE JIRO , NINOMIYA KAZUKI , UCHIUMI NORIO , GION MASAHIRO
IPC分类号： H03K19/0175
摘要： PURPOSE:To reduce the through current by limiting a current made flow between the drains of a pair of transistors for driving whose polarities are mutually different by a current limiting means. CONSTITUTION:The current limiting means 100 limits the current made flow between the drain of a first P-channel transistor 101 and the drain of a first N-channel transistor 104. Thus, a potential difference is generated between the gate of a second P-channel transistor 102 connected to the drain of the first P-channel transistor 101 and the gate of a second N-channel transistor 105 connected to the drain of the first N-channel transistor 104. Thus, by shifting the driving timings of the second P-channel transistor 102 and the second N- channel transistor 105 as the transistors for output, the time when both second P-channel transistor 102 and second N-channel transistor 105 are turned to an on state is shortened.

2. 发明专利

JPH07160740A LAYOUT DESIGN DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH07160740A
公开(公告)日：1995-06-23
申请号：JP30510293
申请日：1993-12-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO , YAMAGUCHI SEIJI
IPC分类号： G06F17/50
摘要： PURPOSE:To provide the layout design device for semiconductor integrated circuit which detects a design rule error like a slit in the stage of design to automatically correct it. CONSTITUTION:This layout design device for semiconductor integrated circuit is provided with a means 108 which detects the slit generated between layout data 100 and 101 of a second semiconductor integrated circuit which is in the same layer as first layout data 102 and has electric connection to first layout data at each time of arranging the layout data 102 or a first semiconductor integrated circuit, a means 112 which uses the same layer as layout data 100 to 102 of first and second layout data to fill up the slit, and means 109, 111, and 113 which generate electric connection between the slit and layout data of the first semiconductor integrated circuit.

3. 发明专利

JPH05298092A 失效
公开(公告)号：JPH05298092A
公开(公告)日：1993-11-12
申请号：JP9651792
申请日：1992-04-16
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： G06F9/38
摘要： PURPOSE:To accelerate the out-of-order execution speed of instructions. CONSTITUTION:A first buffer group 3 consisting of four entry buffers A, B, C, and D is provided in order to enable the out-of-order execution of instructions. A second buffer group 20 is provided so that entries of buffers C and D are saved in the case that instructions stored in buffers A and B in the first buffer group 3 have mutual flow depending relations and instructions stored in buffers C and D of the first buffer group 3 are already executed in advance. Thus, the succeeding instruction are stored into the first buffer group 3 and the execution in advance is available.

4. 发明专利

JPH03251910A SEMICONDUCTOR INTEGRATED CIRCUIT AND CHANGING METHOD FOR CLOCK TIME WIDTH 失效
公开(公告)号：JPH03251910A
公开(公告)日：1991-11-11
申请号：JP4974990
申请日：1990-03-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： G06F1/04 , G06F1/06 , G06F1/10 , G06F1/12 , H03K5/04
摘要： PURPOSE:To transfer data at a high speed by providing plural latches having different threshold voltage levels of the inputs of the clocks having the different time widths at different voltage levels and the binary logic circuits having the transmission time larger than the clock period. CONSTITUTION:The time (t) when a clock phi1 started is set at '0', and logic value '1' is inputted via the IN. A latch 10 fetches the logic value '1' inputted at t = T/12 when the voltage of the clock phi1 exceeds a threshold level VT2. The output (a) of the latch 10 is inputted to a binary logic circuit 40, and the output (b) of the circuit 40 is set at logic value '1' at t = 27*T/24. The logic value '1' inputted to a latch 20 is fetched when the input voltage exceeds a threshold level VT1, i.e., at t = 7*T/6. The output (c) is inputted to a binary logic circuit 50, and the output (d) is set at logic value '1' at t = 4*T/3. A latch 30 fetches the inputted logic value '1' when the voltage of the clock phi1 exceeds the level VT2. The time required for transmission of the logic value '1' to the OUT from the IN is equal to 25*T/12. Thus, the logic value can be transmitted at a high speed and with high efficiency.

5. 发明专利

JP2005157740A Microcomputer 审中-公开
标题翻译：微机
公开(公告)号：JP2005157740A
公开(公告)日：2005-06-16
申请号：JP2003395325
申请日：2003-11-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAGIRA YASUHIRO , ITO YUTAKA , UCHIUMI NORIO
IPC分类号： G06F12/14 , G06F1/00 , G06F15/78 , G06F21/22
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer capable of reading predetermined necessary programs or data among data of an incorporated non-volatile memory from an external memory space, and also improving security for the reading of programs or data which should be made secret. SOLUTION: In this microcomputer 100, an incorporated non-volatile memory 120 is provided with three storage regions for storing programs and data, and an area register 140 stores whether to permit the reading of programs or data for each of the storage regions of the incorporated non-volatile memory 120, and a comparing means 150 compares whether or not a reading non-permitting region stored in the area register 140 is matched with the storage region to be accessed by a CPU 110, and when the comparison result is coincidence, a data invalidating means 160 invalidates the programs or data read from the incorporated non-volatile memory 120. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够从外部存储器空间读取所组合的非易失性存储器的数据之间的预定必要程序或数据的微计算机，并且还提高了应该进行的程序或数据的读取的安全性秘密。解决方案：在微计算机100中，并入的非易失性存储器120具有用于存储程序和数据的三个存储区域，并且区域寄存器140存储是否允许读取每个存储区域的程序或数据并且比较装置150比较存储在区域寄存器140中的读取不允许区域是否与要由CPU 110访问的存储区域相匹配，并且当比较结果为数据无效装置160使从所合并的非易失性存储器120中读取的程序或数据无效。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JPH11175497A INFORMATION PROCESSOR 失效
公开(公告)号：JPH11175497A
公开(公告)日：1999-07-02
申请号：JP34046097
申请日：1997-12-11
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ITO YUTAKA , UCHIUMI NORIO
IPC分类号： G11C17/00 , G06F3/05 , G06F9/06 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide an information processor for realizing high speed data rewriting on a substrate while it is mounted in an information processor incorporating a rewritable non-volatile memory. SOLUTION: An analog input signal 115 inputted from a PROM writer 109 is converted into a digital signal by A/D converters 1041, 1042, and 1043, while a majority decision circuit 1044 determines and holes one digital data according to majority decision logic from among three data digital-converted by the A/D converters 1041, 1042 and 1043, and a CPU 101 decodes the digital data held in the majority decision circuit 1044, and rewrites a non-volatile memory 102.

7. 发明专利

JPH07114432A PRECHARGE DEVICE 失效
公开(公告)号：JPH07114432A
公开(公告)日：1995-05-02
申请号：JP26076193
申请日：1993-10-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYAKE JIRO , NINOMIYA KAZUKI , TOYOKURA MAKI , UCHIUMI NORIO , GION MASAHIRO
IPC分类号： G11C11/41 , G06F3/00
摘要： PURPOSE:To reduce power consumption by detecting a threshold level of transistors (TRs) to terminate precharging thereby decreasing a precharge potential to a signal line and decreasing a time required for pre-charging and an output time of a signal to the signal line. CONSTITUTION:This device is provided with a detection circuit 2 comprising a P-channel MOS TR 7 and N-channel MOS TRs 4, 5 connected in series and a precharge control circuit 3 comprising a P-channel MOS TR 10, a NAND circuit 8 and a delay circuit 11. And a control signal is given to gates of the TRs 7, 4 and the control circuit 11, the output of the delay circuit 11 and a signal line 6 detecting a threshold level VT with the TR 5 whose gate connects to a signal line l9, is inputted to the NAND circuit 8, its output is given to a gate of the TR 10 to control precharging of the signal line 19.

8. 发明专利

JP2008027341A Instruction set and information processor 审中-公开
标题翻译：指令集和信息处理器
公开(公告)号：JP2008027341A
公开(公告)日：2008-02-07
申请号：JP2006201921
申请日：2006-07-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UCHIUMI NORIO
IPC分类号： G06F9/30
CPC分类号： G06F9/30178 , G06F9/30156
摘要： PROBLEM TO BE SOLVED: To improve the parallelism of a program by a relatively simple means.
SOLUTION: A system is provided, which allocates at least one mnemonic or more in dependence upon at least one or more operation codes around the operation code of a present execution target instruction in addition to a mnemonic allocated to the operation code of the present execution object instruction of a program. Consequently the object size of the program can be compressed by increasing the number of instructions definable by the same instruction code width. Therefore, it is possible to achieve an excellent instruction set in which the parallel property of the program can be improved by a relatively simple means.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过相对简单的方法来提高程序的并行性。解决方案：提供一种系统，该系统除了分配给操作代码的助记符之外，还依赖于当前执行目标指令的操作代码周围的至少一个或多个操作代码来分配至少一个助记符或更多个助记符当前程序的执行对象指令。因此，可以通过增加由相同指令代码宽度定义的指令的数量来压缩程序的对象大小。因此，可以通过相对简单的手段来实现能够提高程序的并行性的优异的指令集。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JPH1187515A SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTILAYER WIRING STRUCTURE 失效
公开(公告)号：JPH1187515A
公开(公告)日：1999-03-30
申请号：JP24868197
申请日：1997-09-12
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： H01L21/82
摘要： PROBLEM TO BE SOLVED: To enable a wiring region located between semiconductor logic blocks to be lessened in width so as to lessen an LSI chip in area by a method wherein the LSI chip has a multilayer wiring structure where terminals on the layout of the semiconductor logic blocks are arranged at arbitrary locations. SOLUTION: A first and a second metal wiring layer are connected together in a block, and a first and a second semiconductor logic circuit are laid out on an LSI chip. The first and second semiconductor logic block are wired by the use of the wiring of the wiring layer based on logic connection data as to functional blocks, the horizontal connection of the blocks is made with a third metal wiring, and the horizontal connection of the blocks is made with a fourth metal wiring. The terminals of the semiconductor logic blocks located on the right and left side of the layout of the logic blocks are led out in a horizontal direction with the third metal wiring, and the terminals located on the upper and lower side of the layout are led out in a vertical direction with the fourth metal wiring. By this setup, a wiring region located between the first and second semiconductor logic block is lessened in width, whereby the LSI chip can be lessened in area.

10. 发明专利

JPH04182832A INSTRUCTION PREFETCH DEVICE AND INFORMATION PROCESSOR 失效
公开(公告)号：JPH04182832A
公开(公告)日：1992-06-30
申请号：JP31355690
申请日：1990-11-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： G06F9/38
摘要： PURPOSE:To output a jump destination address in a 2nd cycle by detecting a branch instruction among instructions stored in an instruction buffer and outputting the address which is calculated by an adder for branch destination address calculation in the 2nd cycle. CONSTITUTION:For example, an instruction A is an instruction other than the branch instruction and an instruction B is the branch instruction. In a 1st cycle, an address, the instruction A, and the instruction B are stored in buffers 10, 20, and 30 respectively. A branch instruction detection device 40 detects the instruction B being the branch instruction and the adder 60 calculates the address. In the 2nd cycle, an adder 70 adds the address stored in the buffer 10 and a value entered into the instruction B previously to calculate the address of the jump destination of the branch instruction and a branch destination instruction request signal 130 becomes 1. Thus, this instruction prefetch device fetches the two instructions at the same time and outputs the address of the jump destination of the branch instruction from the processor before the address is selected by using a branch establishment signal, so the address can be outputted in the 2nd cycle after the branch instruction is fetched.

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