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1. 发明专利

JP2007110237A Interface circuit 审中-公开
标题翻译：接口电路
公开(公告)号：JP2007110237A
公开(公告)日：2007-04-26
申请号：JP2005296608
申请日：2005-10-11
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NINOMIYA KAZUKI
IPC分类号： H03K19/0175 , H01L21/822 , H01L27/04 , H03K17/08
摘要： PROBLEM TO BE SOLVED: To obtain an interface circuit in which the internal circuit is protected against a surge when power is turned on, and a leak current can be reduced when power is turned off even when a connected external circuit is turned on. SOLUTION: A transistor 109 for interrupting the leak current is provided between a protection circuit 103 and a power supply (VDD). Furthermore, a transistor 110 for interrupting the leak current is provided between a transistor 102 for driving an external signal I/O terminal to a High level when a High level signal is outputted and the power supply (VDD). A voltage higher than a voltage of the power supply (VDD) is applied to each gate terminal of two leak current interruption transistors by a step-up circuit 111. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了获得接通电路，其中当电源接通时内部电路被保护以防止浪涌，并且即使连接的外部电路被接通而断电时也可以减少漏电流。解决方案：在保护电路103和电源（VDD）之间设置用于中断漏电流的晶体管109。此外，当输出高电平信号时，在用于驱动外部信号I / O端子的晶体管102提供到高电平的晶体管102和电源（VDD）之间，设置用于中断漏电流的晶体管110。通过升压电路111将高于电源电压（VDD）的电压施加到两个漏电流中断晶体管的每个栅极端子。（C）2007，JPO＆INPIT

2. 发明专利

JP2005038551A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2005038551A
公开(公告)日：2005-02-10
申请号：JP2003276691
申请日：2003-07-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NINOMIYA KAZUKI
IPC分类号： G11C11/41
摘要： PROBLEM TO BE SOLVED: To reduce a required area by sharing an address decoder and the like at each port in a multi-port structured semiconductor storage device which is used for video processing, for example.
SOLUTION: A memory cell array is divided into two memory blocks 106 and 108, for example. A selection means A is provided to select and output any one of address signals of each port and control signals 101 and 102. The selection means A assigns the address signals of each port and the control signals 101 and 102 to each memory block for decoders 104 and 105 of the memory blocks 106 and 108 so that an access object of each port does not become a same memory block. For example, address signals of a port 1 for the memory block 106 and address signals of a port 2 for the memory block 108 are simultaneously assigned, respectively. Thus, two memory blocks 106 and 108 are provided with one decoder 104 and one decoder 105, respectively.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：例如，通过在用于视频处理的多端口结构化半导体存储设备中的每个端口处共享地址解码器等来减少所需区域。解决方案：例如，存储单元阵列被分成两个存储器块106和108。提供选择装置A以选择和输出每个端口的地址信号和控制信号101和102中的任何一个。选择装置A将每个端口的地址信号和控制信号101和102分配给每个用于解码器104的存储块和105的存储器块106和108，使得每个端口的访问对象不变成相同的存储块。例如，分别同时分配用于存储块106的端口1的地址信号和存储块108的端口2的地址信号。因此，两个存储器块106和108分别设置有一个解码器104和一个解码器105。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPH08106531A METHOD AND DEVICE FOR PICTURE PROCESSING 失效
公开(公告)号：JPH08106531A
公开(公告)日：1996-04-23
申请号：JP24137394
申请日：1994-10-05
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HASEGAWA KATSUYA , MIYAKE JIRO , NINOMIYA KAZUKI , NISHIYAMA TAMOTSU
IPC分类号： H04N7/015 , G06F17/10 , G06T1/60 , G06T9/00
摘要： PURPOSE: To perform real-time processing in the picture processor which programmably processes video signals of plural broadcast systems and signal forms by single hardware. CONSTITUTION: A vector register part 2 where picture data is stored, a load store part 1 which reads out and writes contents of the vector register from and in an external memory 5, a program decoding part 3 where a picture processing program is stored, and function block parts 6 to 15 which process plural fundamental operations common to plural signal processing systems in parallel are provided. Instructions constituting the picture processing program designate the operations of block (6 to 15) units and the operation of the load store part 1. By this constitution, video signals in plural broadcast systems and signal forms are processed in real time by single hardware, namely, processor.

4. 发明专利

JPH07114432A PRECHARGE DEVICE 失效
公开(公告)号：JPH07114432A
公开(公告)日：1995-05-02
申请号：JP26076193
申请日：1993-10-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYAKE JIRO , NINOMIYA KAZUKI , TOYOKURA MAKI , UCHIUMI NORIO , GION MASAHIRO
IPC分类号： G11C11/41 , G06F3/00
摘要： PURPOSE:To reduce power consumption by detecting a threshold level of transistors (TRs) to terminate precharging thereby decreasing a precharge potential to a signal line and decreasing a time required for pre-charging and an output time of a signal to the signal line. CONSTITUTION:This device is provided with a detection circuit 2 comprising a P-channel MOS TR 7 and N-channel MOS TRs 4, 5 connected in series and a precharge control circuit 3 comprising a P-channel MOS TR 10, a NAND circuit 8 and a delay circuit 11. And a control signal is given to gates of the TRs 7, 4 and the control circuit 11, the output of the delay circuit 11 and a signal line 6 detecting a threshold level VT with the TR 5 whose gate connects to a signal line l9, is inputted to the NAND circuit 8, its output is given to a gate of the TR 10 to control precharging of the signal line 19.

5. 发明专利

JPH05151083A LRU CIRCUIT 失效
公开(公告)号：JPH05151083A
公开(公告)日：1993-06-18
申请号：JP31053591
申请日：1991-11-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NINOMIYA KAZUKI
IPC分类号： G06F12/10 , G06F12/12 , G11C7/00
摘要： PURPOSE:To prevent deterioration in performance due to replacement by setting a lock bit in the LRU circuit and inhibiting the replacement with the lock bit when a TLB, etc., are used by a replacement control circuit. CONSTITUTION:The LRU circuit has a register 2 which holds an LRU value indicating a history of use and a register 15 which holds the lock bit from outside by setting or resetting; and a comparator 5 compares inputs and compares the values of the registers 2 and 5 with the value of an LRU line inputted from outside to output a large/small detection signal or coincidence signal and whether or not the replacement is allowed is determined according to the output of the comparator 5 to disables data having the lock bit from being replaced.

6. 发明专利

JP2008185443A Semiconductor inspection device 审中-公开
标题翻译：半导体检测装置
公开(公告)号：JP2008185443A
公开(公告)日：2008-08-14
申请号：JP2007018971
申请日：2007-01-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NINOMIYA KAZUKI
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To determine poor connection in mounting inspection of an LSI to be inspected without adding a complicated circuit.
SOLUTION: Both a power supply voltage VDD and a ground voltage VSS of the LSI 38 to be inspected and mounting LSIs 39 and 40 are set at 0 V, and a positive inspection power supply voltage VDDT is supplied to the LSI 38 to be inspected, thereby applying positive potential to terminals 3 and 4 to be inspected from the inside. Current flows through a protective circuit 23 on the power supply side in the mounting LSI 39 as a connection destination at the terminal 3 having no poor connection, so that the potential of the terminal 3 decreases. The potential of the terminal 4 having no poor connection does not decrease. The potential variation appearing in the terminals 3 and 4 to be inspected according to the existence of the poor connection is determined, thereby performing connection inspection.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了确定要检查的LSI的安装检查中的连接不良而不增加复杂的电路。解决方案：要检查的LSI 38的电源电压VDD和接地电压VSS以及安装LSIs 39和40均设置为0V，并且将正检查电源电压VDDT提供给LSI 38至检查端子3和4的正电位从内部检查。电流作为连接目的地流过安装LSI 39的电源侧的保护电路23，端子3的连接不良，使得端子3的电位降低。连接不良的终端4的电位不降低。确定根据连接不良而要检查的端子3和4中出现的电位变化，从而进行连接检查。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005055236A Inspection device of semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路检测装置
公开(公告)号：JP2005055236A
公开(公告)日：2005-03-03
申请号：JP2003284597
申请日：2003-08-01
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KODERA KEISUKE , OCHIAI TOSHIYUKI , NINOMIYA KAZUKI , ATOI YOSHIYUKI
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide wiring for connecting a semiconductor integrated circuit and an external circuit through a socket, and to provide an inspection device of the semiconductor integrated circuit for inspecting the connected state between the external connection terminals of the semiconductor integrated circuit connected to the external circuit in the inspection device of the semiconductor integrated device for executing the testing of an entire system including the external circuit.
SOLUTION: A relay 5 is provided between the external circuit 3 and the semiconductor integrated circuit 1, and the connection destination of first wiring 6 is switched to third wiring 8 for connecting the semiconductor integrated circuit 1 and an LSI tester 4 when executing a system test, thus judging whether the connected state between the external connection terminal of the semiconductor integrated circuit 1 and the first wiring 6 is appropriate or not.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供通过插座连接半导体集成电路和外部电路的布线，并且提供用于检查半导体集成电路的外部连接端子之间的连接状态的半导体集成电路的检查装置电路连接到半导体集成装置的检查装置中的外部电路，用于执行包括外部电路的整个系统的测试。解决方案：在外部电路3和半导体集成电路1之间设置有继电器5，并且当执行时将第一布线6的连接目的地切换到用于连接半导体集成电路1和LSI测试器4的第三布线8 系统测试，从而判断半导体集成电路1的外部连接端子与第一布线6之间的连接状态是否适合。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2003264754A SIGNAL PROCESSOR AND SIGNAL PROCESSING METHOD 审中-公开
公开(公告)号：JP2003264754A
公开(公告)日：2003-09-19
申请号：JP2003102689
申请日：2003-04-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NINOMIYA KAZUKI , NISHIYAMA TAMOTSU , MIYAKE JIRO , HASEGAWA KATSUYA
IPC分类号： H04N5/14 , H04N5/46
摘要： PROBLEM TO BE SOLVED: To process signals at a frequency higher than the sampling frequency of video signals while maintaining input-to-output synchronization. SOLUTION: On the input side and output side of a processor 3, frame memories 2 and 4 are arranged, respectively. An input side memory controller 10 detects synchronizing signals from the video signals and updates the write address 14 of the input side frame memory 2 according to the detected synchronizing signal. An output side memory controller 13 updates the read address 15 of the output side frame memory 4 in synchronism with a timing signal 16 from the input side memory controller 10. The processor 3 processes pixel data in the input side frame memory 2 at an operation frequency higher than the sampling frequency of the video signals regardless of the synchronizing signals and stores the result of the process into the output side frame memory 4. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2003036283A Logical simulation device and its method 审中-公开
标题翻译：逻辑仿真器件及其方法
公开(公告)号：JP2003036283A
公开(公告)日：2003-02-07
申请号：JP2001224132
申请日：2001-07-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TOMIOKA SHINICHI , NINOMIYA KAZUKI
IPC分类号： G01R31/28 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a highly-precise logical simulation device and to reduce a verification period in logical simulation by taking into consideration the simulation execution sequence of sequence circuits whose output signal is a clock signal.
SOLUTION: The logical simulation device according to this invention comprises a selection means 2 for selecting from sequence circuits only those sequence circuits whose output is a clock signal, a preceding means 3 for preprocessing logical simulation of the sequence circuits selected by the selection means 2, and a continuation means 4 for executing the logical simulation of other sequence circuit configurations.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供高精度的逻辑模拟装置，并通过考虑其输出信号是时钟信号的序列电路的仿真执行序列来减少逻辑仿真中的验证周期。解决方案：根据本发明的逻辑模拟装置包括一个选择装置2，用于从序列电路中仅选择输出为时钟信号的那些序列电路，用于预处理由选择装置2选择的序列电路的逻辑仿真的先前装置3，以及用于执行其他顺序电路配置的逻辑仿真的延续装置4。

10. 发明专利

JPH07123337A SIGNAL PROCESSOR 失效
公开(公告)号：JPH07123337A
公开(公告)日：1995-05-12
申请号：JP19504294
申请日：1994-08-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYAKE JIRO , NISHIYAMA TAMOTSU , HASEGAWA KATSUYA , NINOMIYA KAZUKI
IPC分类号： H04N5/46 , G06T1/20
摘要： PURPOSE:To share one hardware for image processing among plural broadcasting systems or plural processing algorithms. CONSTITUTION:This processor is provided with a bus switch 9 equipped with plural input data lines connected to the respective output terminals of; plural computing elements 1-4 respectively provided with basic functions such as filtering functions, one external input data line at least, plural output data lines connected to the.respective input terminals of the computing elements 1-4 and one external output data line at least so as to variously connect the respective computing elements 1-4. Further, the device is provided with two register sets 13a and 13b for respectively holding arithmetic control information to designate the processing contents of the computing elements 1-4 and connection control information to designate the connection conditions inside the bus switch 9. Corresponding to the broadcasting system, the held information in both register sets 13a and 13b is updated and corresponding to the processing algorithm, either one of both register sets 13a and 13b is selected.

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