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1. 发明专利

JPS61177768A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61177768A
公开(公告)日：1986-08-09
申请号：JP1857185
申请日：1985-02-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KONDO SHIZUO , HAIJIMA MIKIO , HINO TETSURO , AKAMATSU YOSHINORI
IPC分类号： H01L29/08 , H01L21/8222 , H01L27/02 , H01L27/082
摘要： PURPOSE:To obtain the IIL of low consumed power by improving the factor of injector current utilization, by a method wherein p-type regions serving as the injector are formed as two p-type regions isolated from each other, and an injector electrode is provided across these two p-type regions, so as to cover therebetween. CONSTITUTION:A p type Si substrate 11 is provided with an n type buried layer 12 serving as the emitter of a multicollector transistor, an n type epitaxial layer 13 grown on the substrate 11, a p-type diffused layer 14 serving as the base of the multicollector transistor, and a plurality of shallow n type diffused layers 15 serving as multicollectors. Window holes are bored in an Si oxide film 18, these regions are provided with electrodes 19, 20 made of aluminum evaporated films by low-resistant connection. Among these the elec trode 20 connected to p-type diffused layers 16, 17 is provided across them so as to cover therebetween.

2. 发明专利

JPS61150231A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61150231A
公开(公告)日：1986-07-08
申请号：JP27092684
申请日：1984-12-24
申请人： HITACHI MICROCUMPUTER ENG , AKITA DENSHI KK , HITACHI LTD
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , IHARA HIROSHI
IPC分类号： H01L21/764 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L29/73 , H01L29/732
摘要： PURPOSE:To prevent a parasitic PNP transistor from being formed, to improve characteristics of a transistor, and to manufacture the IC operating stably, by forming an N -type diffusion layer extended from an N -type buried layer between an N -type semiconductor region and an isolation P-type layer. CONSTITUTION:An N -type buried layer 2 is extended to below an isolation groove 4, and an N -type diffusion layer 9 with a high concentration is formed between the periphery of an N -type mesa semiconductor region 3a and an N -type buried layer extension. A portion of the N -type diffusion layer 9 serves as a collector taking-out section 8 where a collector electrode C is provided in a groove. In an IC structure having an NPN transistor so constructed, its base would be coupled to the isolation P-type diffusion layer in the peripheral groove when being saturated to result in a parasitic PNP sub-transistor. However, by forming the N -type diffusion layer 9 with a high concentration on the periphery acting as the base of the PNP sub-transistor, amplification factor alphaof the PNP sub-transistor is reduced and thus its operation is prevented. In this way, transistor characteristics can be improved and the transistor can be operated at a low consuming power.

3. 发明专利

JPS61218157A RESISTOR 失效
公开(公告)号：JPS61218157A
公开(公告)日：1986-09-27
申请号：JP5841585
申请日：1985-03-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TAKIGAWA AKIRA , KONDO SHIZUO , KASAHARA MASUMI , HIRASHIMA TOSHINORI , HAIJIMA MIKIO , OGURA SADAO
IPC分类号： H01C7/00 , H01L21/822 , H01L27/04 , H03M1/12
摘要： PURPOSE:To improve the ratio accuracy when a ladder type is particularly formed by forming the corners of a thin film resistor of bent flat pattern at an obtuse angle. CONSTITUTION:A thin film resistor R1 is formed by photoetching a metal resistor 1 made of aluminum or the like in a semiconductor integrated circuit device, and to increase the resistance value, the flat pattern shape is bent in a zigzag shape. The corners 1A, 1B of the pattern are formed at obtuse angle (approx. 135 deg.). Thus, a deformation due to etching is hardly laterally presented, to improve the product accuracy.

4. 发明专利

JPS61220449A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61220449A
公开(公告)日：1986-09-30
申请号：JP6064285
申请日：1985-03-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAIJIMA MIKIO , ISHIKAWA MAKOTO , TAKIGAWA AKIRA , KONDO SHIZUO , TANIZAKI YASUNOBU
IPC分类号： H01L21/822 , H01L21/8226 , H01L27/02 , H01L27/04 , H01L27/082
摘要： PURPOSE:To obtain a highly integrated, highly reliable device, by forming a recess part in the surface of a chip, forming a thin digital circuit in the inner part, forming a thick analog circuit at the peripheral pat in a concentrated manner, implementing high speed and high performance of the digital circuit, and implementing high withstanding voltage of the analog circuit. CONSTITUTION:An n epitaxial layer 2 is provided on a p substrate 1, in which an n layer 3 is embedded. Selective etching is performed and a recess part 4 is formed at the central part. The central part 5 of the layer 2 is thin, and a peripheral part 6 is thick. A digital element such as I L is provided at the thin central part. The impurity distribution in the cross section of a transistor in the reverse direction is formed in a steep form. An operating margin is made high and the high speed I L is implemented. Meanwhile a bipolar n-p-n transistor at a linear part is formed in the thick peripheral part 50 that enough withstanding voltage is provided. In this configuration, stepped parts due to the irregularities of the surface are reduced, and wire breakdowns are decreased. This is especially useful when an organic insulating film is formed on the surface and multilayer wiring is provided.

5. 发明专利

JPS60152052A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60152052A
公开(公告)日：1985-08-10
申请号：JP709784
申请日：1984-01-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAIJIMA MIKIO , OGURA SADAO , KONDOU SHIZUO , WATABE TOMOYUKI , HAYASHI MAKOTO
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082
摘要： PURPOSE:To make each characteristic of an analog element and a digital element to coexist mutually without complicating processes by additionally doping a conductive impurity into a forming region for the digital element selectively. CONSTITUTION:An n type epitaxial layer 12 in comparatively low impurity concentration in an analog element forming region a1 is used as it is, thus forming an npn bipolar transistor Q1. On the other hand, an n type conductive impurity is additionally doped selectively into the n type epitaxial layer 12 in comparatively low concentration in a digital element forming region a2, thus forming an IIL. The effective impurity concentration of the layer 12 in the region a2 is increased relatively because an n type diffusion layer 20 is diffused additionally into the low-concentration n type epitaxial layer 12. Accordingly, each characteristic of an analog element and a digital element can be made to coexist and improved mutually without complicating processes.

6. 发明专利

JPS60226158A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60226158A
公开(公告)日：1985-11-11
申请号：JP8186784
申请日：1984-04-25
申请人： AKITA DENSHI KK , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IHARA HIROSHI , TAKIGAWA AKIRA , HAIJIMA MIKIO , WASHIO KATSUYOSHI , WATABE TOMOYUKI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
摘要： PURPOSE:To obtain an electrostatic breakdown preventing element to fit to a high integration process of IC by a method wherein the element is constitued in such a structure that the transistor consisting of the n type semiconductor layer, which is used as the base, either of the p type resistance region or the p type substrate, which is used as the emitter, and the other one, which is used as the collector, is actuated and surge pulse is absorbed. CONSTITUTION:When a forward surge pulse (+) is impressed on an electrode 12a on the side of the input terminal, surge current runs momentarily in the interior of a p type layer 9, voltage drop is caused by resistance in the interior of the p type layer9 p-n forward voltage is added in between the p type layer 9 and an n type region 6a. A p-n-p transistor Q1 consisting of the layer 9, which is used as its emitter, the region 6a, which is used as its base, and a p type substrate 4, which is used as its collector, is actuated to make positive surge escape rapidly to the earth potential. Meanwhile, when inverse surge pulse (-) is impressed on the electrode 12a on the side of the input terminal, an inverse p-n-p subtransistor Q2 consisting of the p type substrate 4, which is used as its emitter, the n type region 6a, which is used as its base, and the p type diffusion layer 9, which is used as the collector, is actuated and negative pulse is absorbed.

7. 发明专利

JPH0316241A SEMICONDUCTOR DEVICE AND AUTOMATIC FORMATION OF WIRING THEREOF 失效
公开(公告)号：JPH0316241A
公开(公告)日：1991-01-24
申请号：JP14963489
申请日：1989-06-14
申请人： HITACHI LTD
发明人： SATO YASUO , YUYAMA YASUSHI , KAWAJI MOTONORI , HAIJIMA MIKIO
IPC分类号： H01L21/82 , G06F17/50
摘要： PURPOSE:To improve the reliability and the yield by enlarging wiring pitches at the place where the ground step difference at a cell part is great, and at the place where wiring complication degree is low. CONSTITUTION:A logical LSI chip 100 is the one where the wiring width W of metallic layer wiring 4 in the ground step region of a semiconductor element part 3 (all row) is made large and wiring interval (pitch) P is made large in the place where wiring complication degree is low. If the wiring width W of the logical LSI chip 100 is widened or the wiring pitch P is widened, the yield rate in metallic wiring formation at the ground step region of the logical LSI chip 100 can be improved. Hereby, the reliability and the yield of LSI can be improved.

8. 发明专利

JPS63232364A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63232364A
公开(公告)日：1988-09-28
申请号：JP6392387
申请日：1987-03-20
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , INABA TORU
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/02 , H01L27/06 , H01L29/732
摘要： PURPOSE:To improve electrostatic breakdown resistance strength of a semiconductor device without decreasing an integration by increasing a length between the base electrode connector of a first bipolar transistor connected to a pad and an emitter region larger than that of a second bipolar transistor connected directly to the pad. CONSTITUTION:In a semiconductor device in which at least one of outer terminals PAD of the base and the emitter of a bipolar first transistor Q1 formed on one main surface of a semiconductor substrate and the other is connected to the internal circuit of the same substrate, a distance l1 between a base electrode contact and an emitter region is a distance l2 or longer between the base electrode contact and the emitter region of a second transistor Q1 not connected to an outer terminal formed at the other surface of the substrate to be preferably twice or longer. Thus, an interval between the base electrode and the emitter electrode is broadened to increase the values of parasitic resistance and capacity to largely improve electrostatic breakdown resistance strength.

9. 发明专利

JPS63204640A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS63204640A
公开(公告)日：1988-08-24
申请号：JP3552587
申请日：1987-02-20
申请人： HITACHI LTD
发明人： INABA TORU , HAIJIMA MIKIO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/8222 , H01L27/06 , H01L29/80
摘要： PURPOSE:To obtain a means, with which a bipolar static induction transistor (SIT) having high-speed and large-current characteristics can coexist as part of an IC, by a method wherein p-type buried layers are arranged in a mesh shape in contact to an n buried layer in one semiconductor insular region isolated. CONSTITUTION:In the structure formed in an insular region II, mesh-shaped p-type buried layers 6 are formed on an n buried layer 3. Therefore, one of the layers 6 is connected with a p-type layer 12 to be formed by base diffusion and a gate electrode can be led out. By applying bias between the layer 12 and an n-type epitaxial layer, a depletion layer extends to the periphery of the p-type layer, the switching ON and the switching OFF of current between a source (n layer 16) and a drain (n layer 14) are operated and a vertical type SIT having high-speed and large-current switch characteristics can be obtained by a process for microscopical formation. The mesh- shaped p-type buried layer which is used as the gate electrode can be formed simultaneously with p-type buried layers for isolation and the p-type layer for leading out the gate electrode can be diffused simultaneously with the p-type layer which is used as a base. Thereby, an IC, in which the SIT and an n-p-n transistor coexist, can be obtained without increasing specially the manhour.

10. 发明专利

JPS62105463A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62105463A
公开(公告)日：1987-05-15
申请号：JP24397185
申请日：1985-11-01
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , INABA TORU
IPC分类号： H01L21/822 , G11C11/401 , G11C11/407 , H01L21/8238 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/092
摘要： PURPOSE:To reduce remarkably power consumption by dividing a CMOS circuit into a plurality of semiconductor region, making each of the semiconductor regions electrically independent, and connecting electric power sources in each semiconductor region in series for power supplying. CONSTITUTION:In CMOS circuit parts 1 and 2, many CMOS logic circuits composed of a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are formed. Each of the CMOS circuit parts 1 and 2 is formed electrically independently with each other, whose electric power source inputs are connected in series, and a source voltage Vcc1 is supplied from the both ends of this series connection. Thus a source current i1 flows to the ground potential through the CMOS circuit parts 1 and 2. An interface (I/F) part 3 is driven directly by the original high source voltage Vcc1, and contains the functions of level-shift and level-conversion, which convert the output and input signal levels of each of the CMOS circuits 1 and 2 into the ordinary CMOS levels. The power consumption of CMOS circuits formed in a semiconductor integrated circuit device can be remarkably reduced, thereby.

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