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1. 发明专利

JPH0316241A SEMICONDUCTOR DEVICE AND AUTOMATIC FORMATION OF WIRING THEREOF 失效
公开(公告)号：JPH0316241A
公开(公告)日：1991-01-24
申请号：JP14963489
申请日：1989-06-14
申请人： HITACHI LTD
发明人： SATO YASUO , YUYAMA YASUSHI , KAWAJI MOTONORI , HAIJIMA MIKIO
IPC分类号： H01L21/82 , G06F17/50
摘要： PURPOSE:To improve the reliability and the yield by enlarging wiring pitches at the place where the ground step difference at a cell part is great, and at the place where wiring complication degree is low. CONSTITUTION:A logical LSI chip 100 is the one where the wiring width W of metallic layer wiring 4 in the ground step region of a semiconductor element part 3 (all row) is made large and wiring interval (pitch) P is made large in the place where wiring complication degree is low. If the wiring width W of the logical LSI chip 100 is widened or the wiring pitch P is widened, the yield rate in metallic wiring formation at the ground step region of the logical LSI chip 100 can be improved. Hereby, the reliability and the yield of LSI can be improved.

2. 发明专利

JPS63232364A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63232364A
公开(公告)日：1988-09-28
申请号：JP6392387
申请日：1987-03-20
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , INABA TORU
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/02 , H01L27/06 , H01L29/732
摘要： PURPOSE:To improve electrostatic breakdown resistance strength of a semiconductor device without decreasing an integration by increasing a length between the base electrode connector of a first bipolar transistor connected to a pad and an emitter region larger than that of a second bipolar transistor connected directly to the pad. CONSTITUTION:In a semiconductor device in which at least one of outer terminals PAD of the base and the emitter of a bipolar first transistor Q1 formed on one main surface of a semiconductor substrate and the other is connected to the internal circuit of the same substrate, a distance l1 between a base electrode contact and an emitter region is a distance l2 or longer between the base electrode contact and the emitter region of a second transistor Q1 not connected to an outer terminal formed at the other surface of the substrate to be preferably twice or longer. Thus, an interval between the base electrode and the emitter electrode is broadened to increase the values of parasitic resistance and capacity to largely improve electrostatic breakdown resistance strength.

3. 发明专利

JPS63204640A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS63204640A
公开(公告)日：1988-08-24
申请号：JP3552587
申请日：1987-02-20
申请人： HITACHI LTD
发明人： INABA TORU , HAIJIMA MIKIO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/8222 , H01L27/06 , H01L29/80
摘要： PURPOSE:To obtain a means, with which a bipolar static induction transistor (SIT) having high-speed and large-current characteristics can coexist as part of an IC, by a method wherein p-type buried layers are arranged in a mesh shape in contact to an n buried layer in one semiconductor insular region isolated. CONSTITUTION:In the structure formed in an insular region II, mesh-shaped p-type buried layers 6 are formed on an n buried layer 3. Therefore, one of the layers 6 is connected with a p-type layer 12 to be formed by base diffusion and a gate electrode can be led out. By applying bias between the layer 12 and an n-type epitaxial layer, a depletion layer extends to the periphery of the p-type layer, the switching ON and the switching OFF of current between a source (n layer 16) and a drain (n layer 14) are operated and a vertical type SIT having high-speed and large-current switch characteristics can be obtained by a process for microscopical formation. The mesh- shaped p-type buried layer which is used as the gate electrode can be formed simultaneously with p-type buried layers for isolation and the p-type layer for leading out the gate electrode can be diffused simultaneously with the p-type layer which is used as a base. Thereby, an IC, in which the SIT and an n-p-n transistor coexist, can be obtained without increasing specially the manhour.

4. 发明专利

JPS62105463A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62105463A
公开(公告)日：1987-05-15
申请号：JP24397185
申请日：1985-11-01
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , INABA TORU
IPC分类号： H01L21/822 , G11C11/401 , G11C11/407 , H01L21/8238 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/092
摘要： PURPOSE:To reduce remarkably power consumption by dividing a CMOS circuit into a plurality of semiconductor region, making each of the semiconductor regions electrically independent, and connecting electric power sources in each semiconductor region in series for power supplying. CONSTITUTION:In CMOS circuit parts 1 and 2, many CMOS logic circuits composed of a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are formed. Each of the CMOS circuit parts 1 and 2 is formed electrically independently with each other, whose electric power source inputs are connected in series, and a source voltage Vcc1 is supplied from the both ends of this series connection. Thus a source current i1 flows to the ground potential through the CMOS circuit parts 1 and 2. An interface (I/F) part 3 is driven directly by the original high source voltage Vcc1, and contains the functions of level-shift and level-conversion, which convert the output and input signal levels of each of the CMOS circuits 1 and 2 into the ordinary CMOS levels. The power consumption of CMOS circuits formed in a semiconductor integrated circuit device can be remarkably reduced, thereby.

5. 发明专利

JPS61177768A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61177768A
公开(公告)日：1986-08-09
申请号：JP1857185
申请日：1985-02-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KONDO SHIZUO , HAIJIMA MIKIO , HINO TETSURO , AKAMATSU YOSHINORI
IPC分类号： H01L29/08 , H01L21/8222 , H01L27/02 , H01L27/082
摘要： PURPOSE:To obtain the IIL of low consumed power by improving the factor of injector current utilization, by a method wherein p-type regions serving as the injector are formed as two p-type regions isolated from each other, and an injector electrode is provided across these two p-type regions, so as to cover therebetween. CONSTITUTION:A p type Si substrate 11 is provided with an n type buried layer 12 serving as the emitter of a multicollector transistor, an n type epitaxial layer 13 grown on the substrate 11, a p-type diffused layer 14 serving as the base of the multicollector transistor, and a plurality of shallow n type diffused layers 15 serving as multicollectors. Window holes are bored in an Si oxide film 18, these regions are provided with electrodes 19, 20 made of aluminum evaporated films by low-resistant connection. Among these the elec trode 20 connected to p-type diffused layers 16, 17 is provided across them so as to cover therebetween.

6. 发明专利

JPS61150231A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61150231A
公开(公告)日：1986-07-08
申请号：JP27092684
申请日：1984-12-24
申请人： HITACHI MICROCUMPUTER ENG , AKITA DENSHI KK , HITACHI LTD
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , IHARA HIROSHI
IPC分类号： H01L21/764 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L29/73 , H01L29/732
摘要： PURPOSE:To prevent a parasitic PNP transistor from being formed, to improve characteristics of a transistor, and to manufacture the IC operating stably, by forming an N -type diffusion layer extended from an N -type buried layer between an N -type semiconductor region and an isolation P-type layer. CONSTITUTION:An N -type buried layer 2 is extended to below an isolation groove 4, and an N -type diffusion layer 9 with a high concentration is formed between the periphery of an N -type mesa semiconductor region 3a and an N -type buried layer extension. A portion of the N -type diffusion layer 9 serves as a collector taking-out section 8 where a collector electrode C is provided in a groove. In an IC structure having an NPN transistor so constructed, its base would be coupled to the isolation P-type diffusion layer in the peripheral groove when being saturated to result in a parasitic PNP sub-transistor. However, by forming the N -type diffusion layer 9 with a high concentration on the periphery acting as the base of the PNP sub-transistor, amplification factor alphaof the PNP sub-transistor is reduced and thus its operation is prevented. In this way, transistor characteristics can be improved and the transistor can be operated at a low consuming power.

7. 发明专利

JPS6153770A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6153770A
公开(公告)日：1986-03-17
申请号：JP17496484
申请日：1984-08-24
申请人： Hitachi Ltd
发明人： HAIJIMA MIKIO
IPC分类号： H01L21/331 , H01L21/8224 , H01L27/082 , H01L29/06 , H01L29/10 , H01L29/73
CPC分类号： H01L29/0619 , H01L29/0638 , H01L29/1008
摘要： PURPOSE:To realize a very fine structure with a reduced thickness of the surface insulation oxide film and a reduced distance between diffusion layers, by providing the field of a bipolar transistor with a guard ring in which the concentration of a conductive impurity is selectively increased. CONSTITUTION:A guard ring 61 acts to obstruct the formation of a channel inversion layer in the field section between a p type isolating diffusion layer 7 and a p type collector diffusion layer 81. Accordingly, even if the thickness of a surface insulation oxide film 41 is reduced for the purpose of providing a fine structure, the film is prevented from being effected adversely by parasitic MOSFET. Further, since the ring 61 is interposed between the diffusion layers 7 and 81, the effective current amplification factor of a pnp bipolar transistor TR constituted by the diffusion layer 7, an n type epitaxial layer 2 and the diffusion layer 81 is decreased. In this manner, the distance between the diffusion layer 7 and the diffusion layer 81 can be decreased for the purpose of realizing a fine structure without suffering from adverse effect by a parasitic bipolar TR.
摘要翻译：目的：为了实现具有减小的表面绝缘氧化膜厚度和扩散层之间距离减小的非常精细的结构，通过为双极晶体管的场提供选择性增加导电杂质浓度的保护环。构成：保护环61用于阻碍在ap型隔离扩散层7和ap型集电极扩散层81之间的场区中形成沟道反转层。因此，即使表面绝缘氧化物膜41的厚度减小为了提供精细的结构，防止膜被寄生MOSFET不利地影响。此外，由于环61插入在扩散层7和81之间，所以由扩散层7，n +型外延层2和扩散层81构成的pnp双极晶体管TR的有效电流放大系数减小。以这种方式，为了实现精细结构而不会受到寄生双极性TR的不利影响，扩散层7和扩散层81之间的距离可以减小。

8. 发明专利

JPS6057658A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6057658A
公开(公告)日：1985-04-03
申请号：JP16497183
申请日：1983-09-09
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06
摘要： PURPOSE:To obtain MOS capacitance, which is large per an occupied area, by forming irregularities to the surface of a semiconductor substrate and attaching an electrode through an insulating film. CONSTITUTION:An n layer 8 is buried to the (110) face of a p type Si substrate 1 and an n epitaxial layer 2 is superposed, a CVDSiO2 film 10 is superposed on a surface oxide film 9, windows are bored, and grooves 11 having steep slopes are formed by KOH. An SiO2 film 12 and a resist mask 14a are formed and B ions are implanted, the SiO2 films 9, 12, 10 and the resist 14a removed, and a p isolation layer 13 and an SiO2 film 9a are shaped through heat treatment. the grooves 11 may be formed orthogonally. B ions are implanted and diffused through a resist mask to form a p layer 15, and a novel resist mask 16 is executed and As ions are implanted and diffused to shape an n layer 17. When windows are bored to the SiO2 film 9a and an Al electrode 18 is attached, electrodes A, B function as opposite electrodes having MOS capacitance, and an electrode C is connected to low potential and the potential of a p layer is stabilized. According to the constitution, large MOS capacitance is obtained regardless of a small occupied area.

9. 发明专利

JPS59139681A Schottky barrier diode 失效
标题翻译：肖特基二极管二极管
公开(公告)号：JPS59139681A
公开(公告)日：1984-08-10
申请号：JP1271783
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： HAIJIMA MIKIO
IPC分类号： H01L29/47 , H01L29/872 , H01L29/91
CPC分类号： H01L29/872
摘要： PURPOSE:To reduce the formation of alloy pits at a corner and to contrive the stabilization of a Schottky barrier diode to withstand voltage by a method wherein the figure of the main surface of a Schottky barrier part is formed into a polygon or a circular form surrounded with an obtuse angle. CONSTITUTION:A Schottky barrier diode utilizing the rectifying action of a Schottky barrier, which is created at the contact part between a semiconductor and a metal, is the one whereon a Schottky battier was formed by making a metal 4 such as Al, etc., alloy into one part of the surface of an n type Si layer 3 which was epitaxially grown on a p type Si substrate 1 through the intermediary of an N type buried layer 2. At an Al-Si alloy part 7 to make this Schottky barrier, the acuter the angle of a corner is, the more alloy pits are easy to concentrate at the circumference part of the barrier region, but the corner is obtusely formed (90 deg. 135 deg.) by forming the pattern of the Schottky barrier part into an octagon, the formation of alloy pits at the corner part is equalized, current concentration is prevented, the Vf of the Schottky barrier diode is stabilized and leak current is reduced. Besides, this pattern for the barrier is not always limited to one in an octagon. Patterns in an hexagon and other polygons having a large number of angles or ones in a circular form and a rectangle can be used.
摘要翻译：目的：为了减少拐角处的合金凹坑的形成，并且通过以下方法来设计肖特基势垒二极管的稳定性，其中将肖特基势垒部分的主表面的形状形成为多边形或围绕圆形的方法具有钝角。构成：利用在半导体和金属之间的接触部分处产生的肖特基势垒的整流作用的肖特基势垒二极管是通过制造诸如Al等的金属4形成肖特基阻挡层的肖特基势垒二极管，合金成为n型Si层3的表面的一部分，其通过N +型掩埋层2的介质在外延生长在ap型Si衬底1上。在Al-Si合金部分7至使这个肖特基势垒的角度是角的角度，更多的合金凹坑容易集中在阻挡区域的圆周部分，但是通过形成图案的形状（90度135度），角部被钝化地形成将肖特基势垒部分变成八边形，在拐角部分形成合金凹坑相等，防止了电流集中，使肖特基势垒二极管的Vf稳定，漏电流减小。此外，屏障的这种模式并不总是局限在一个八边形。可以使用具有大量角度的六边形和其他多边形中的图案或圆形和矩形的图案。

10. 发明专利

JPS5833880A SEMICONDUCTOR PHOTODETECTOR 失效
公开(公告)号：JPS5833880A
公开(公告)日：1983-02-28
申请号：JP13152881
申请日：1981-08-24
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , MATSUURA AKIRA
IPC分类号： H01L31/10 , H01L31/11
摘要： PURPOSE:To enhance a photodetector by forming the shallow second conductive type impurity introduce layer on a region isolated from one main surface in the first conductive type semiconductor substrate and using the substrate semiconductor and two P-N junction surfaces with upper and lower surfaces of the layer as a photodetecting region. CONSTITUTION:An N type epitaxial Si layer 1 is formed on a P type substrate 3, is surrounded by a P type isolation layer 4 and is electrically isolated from other element region. A P type layer 5 is formed by B ion implantation in a region isolated from the surface of the layer 1 in such a manner that impurity ion flying distance is deepened by increasing ion implantation energy, for example, up to appox. 200keV, and upper and lower P-N junctions (Xj1, Yj2) are by one ion implantation formed between the layer and an N type Si layer, a light incident from the surface of the element excites electrons-holes at the upper and lower P-N junction surfaces, thereby increasing the sensitivity and the area efficiency and improving the efficiency as a photodetector.

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