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1. 发明专利

JPS60226158A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60226158A
公开(公告)日：1985-11-11
申请号：JP8186784
申请日：1984-04-25
申请人： AKITA DENSHI KK , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IHARA HIROSHI , TAKIGAWA AKIRA , HAIJIMA MIKIO , WASHIO KATSUYOSHI , WATABE TOMOYUKI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
摘要： PURPOSE:To obtain an electrostatic breakdown preventing element to fit to a high integration process of IC by a method wherein the element is constitued in such a structure that the transistor consisting of the n type semiconductor layer, which is used as the base, either of the p type resistance region or the p type substrate, which is used as the emitter, and the other one, which is used as the collector, is actuated and surge pulse is absorbed. CONSTITUTION:When a forward surge pulse (+) is impressed on an electrode 12a on the side of the input terminal, surge current runs momentarily in the interior of a p type layer 9, voltage drop is caused by resistance in the interior of the p type layer9 p-n forward voltage is added in between the p type layer 9 and an n type region 6a. A p-n-p transistor Q1 consisting of the layer 9, which is used as its emitter, the region 6a, which is used as its base, and a p type substrate 4, which is used as its collector, is actuated to make positive surge escape rapidly to the earth potential. Meanwhile, when inverse surge pulse (-) is impressed on the electrode 12a on the side of the input terminal, an inverse p-n-p subtransistor Q2 consisting of the p type substrate 4, which is used as its emitter, the n type region 6a, which is used as its base, and the p type diffusion layer 9, which is used as the collector, is actuated and negative pulse is absorbed.

2. 发明专利

JPS6123356A Apparatus for preventing electrostatic breakdown of semiconductor device 失效
标题翻译：防止半导体器件静电破坏的装置
公开(公告)号：JPS6123356A
公开(公告)日：1986-01-31
申请号：JP14239484
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKIGAWA AKIRA , HAIJIMA MIKIO , IHARA HIROSHI , WATABE TOMOYUKI , WASHIO KATSUYOSHI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0255
摘要： PURPOSE:To absorb both positive and negative surge pulses by forming an n type buried layer as a protection resistance and using a junction diode composed of the n type region and the p type diffused region. CONSTITUTION:When a forward surge pulse enters the electrode in the input terminal side, a voltage drops due to a resistance while a surge current flows into the n type buried layer 5. Thereby, an input voltage is clamped to a value which is equal to a breakdown voltage of the p-n junction diode D1 between the n type region 6a and p type region 9. Namely, holes are implanted to a low potential p type layer 9 from the n type region 6a, causing a current I1 to flow and absorbing a surge pulse. A backward surge current operates the p-n junction diode between the n type region 6a and the p type diffused layer 9 and an input voltage is clamped to a voltage (GND-VF) which is equal to a difference between the ground voltage and forward voltage VF of diode, causing electrons to be implanted to the side of p type diffused layer 9 from the n type region 6a.
摘要翻译：目的：通过形成n +型埋层作为保护电阻并使用由n +型区域和p型扩散区域构成的结二极管来吸收正和负浪涌脉冲。构成：当正向浪涌脉冲进入输入端侧的电极时，在浪涌电流流入n +型埋层5的同时由于电阻而下降，由此，将输入电压钳位到等于n +型区域6a和p型区域9之间的pn结二极管D1的击穿电压。即，从n +型区域6a将空穴注入到低电位p型层9中，导致电流I1流动并吸收浪涌脉冲。反向浪涌电流在n +型区域6a和p型扩散层9之间操作pn结二极管，并且将输入电压钳位到等于接地电压和二极管的正向电压VF，使电子从n +型区域6a注入到p型扩散层9侧。

3. 发明专利

JPS6123355A Apparatus for preventing electrostatic breakdown of semiconductor 失效
标题翻译：防止半导体静电破坏的装置
公开(公告)号：JPS6123355A
公开(公告)日：1986-01-31
申请号：JP14238984
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HAIJIMA MIKIO , TAKIGAWA AKIRA , IHARA HIROSHI , IWASAKI ISAO , WATABE TOMOYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： PURPOSE:To absorb both forward and backward surge pulses by forming an n type buried layer as a protection resistance and allowing an input pulse to escape through utilization of the forward and backward npn transistor comprising an n type semiconductor region, p type diffused region and n type diffused region. CONSTITUTION:When a forward surge pulse enters the electrode in the side of input terminal B, a voltage drops due to a resistance R while a surge current I0 flows in the n type buried layer 5. Thereby, a forward npn transistor Q1 (composed of the n type semiconductor region 6a, p type semiconductor region 9 and n type semiconductor 10) operates and a current I1 flows into the ground electrode passing through the electrode on n type diffused region 10. When a backward surge pulse enters, a negative surge current flows to the side of circuit A through the n type buried layer 5, resulting in voltage drop. Therefore, a backward npn transistor Q2 where the p type region 9 is formed as the base, the n type diffused region 10 as the collector and n type semicondutor region as the emitter operates and a current I2 flows to the side of input terminal B.
摘要翻译：目的：通过形成n +型埋层作为保护电阻并允许输入脉冲通过利用包括n +型半导体区域的正向和反向npn晶体管来逸出来吸收正向和反向浪涌脉冲， p型扩散区和n +型扩散区。构成：当正向浪涌脉冲进入输入端子B侧的电极时，由于电阻R的电压下降，而浪涌电流I0在n +型埋层5中流动。因此，正向npn晶体管Q1 （由n型半导体区域6a，p型半导体区域9和n +型半导体10构成）工作，电流I1流入通过n +型扩散区域10上的电极的接地电极当反向浪涌脉冲进入时，负的浪涌电流通过n +型埋层5流向电路A侧，导致电压下降。因此，作为基极形成p型区域9的后向npn晶体管Q2，作为集电极的n +型扩散区域10和作为发射极的n +型半导体区域工作，电流I2流向输入端B.

4. 发明专利

JPS6123354A Apparatus for preventing electrostatic breakdown of semiconductor device 失效
标题翻译：防止半导体器件静电破坏的装置
公开(公告)号：JPS6123354A
公开(公告)日：1986-01-31
申请号：JP14238884
申请日：1984-07-11
申请人： Akita Denshi Kk , Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： IHARA HIROSHI , HAIJIMA MIKIO , TAKIGAWA AKIRA , WATABE TOMOYUKI , IWASAKI ISAO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： PURPOSE:To improve an electrostatic breakdown level up to about 100V by forming the n type diffused region by diffusion of emitter as a protection resistance and by absorbing the forward and backward surge pulse by allowing an input pulse to escape to Vcc through utilization of the npn transistor consisting of such n type region, p type diffused region and n type region. CONSTITUTION:In case the forward surge pulse enters the electrode in the side of input terminal, a voltage drops due to a resistance R while a surge current Io flows into the n diffused region 10. Thereby, the backward npn transistor, where the n type diffused region 10 used as the collector, the p type diffused region 9 as the base and the n type region 6a as the emitter, operatesk. Since the emitter side is connected to a high voltage side, electrons are implanted to the p type region 9 as the base from the n type region 6a which becomes the emitter, causing a current I1 to flow in order to absorb surge pulse. When the backward surge pulse enters the electrode in the input terminal side, a current I2 flows to the input terminal side from Vcc side, absorbing a surge pulse.
摘要翻译：目的：为了通过扩散发射极作为保护电阻形成n +型扩散区域，并通过允许输入脉冲通过利用来将输入脉冲逸出到Vcc来吸收正向和反向浪涌脉冲，来提高高达约100V的静电击穿电平由n +型晶体管组成的n +型区域，p型扩散区域和n +型区域。构成：在正向浪涌脉冲进入输入端侧的电极的情况下，由于电阻R的电压下降，而浪涌电流Io流入n +扩散区域10.因此，后向npn晶体管，其中用作集电极的n +型扩散区域10，作为基极的p型扩散区域9和作为发射极的n +型区域6a。由于发射极侧连接到高电压侧，因此电子从作为发射极的n +型区域6a注入作为基极的p型区域9，导致电流I1流过以吸收浪涌脉冲。当反向浪涌脉冲进入输入端侧的电极时，电流I2从Vcc侧流向输入端侧，吸收浪涌脉冲。

5. 发明专利

JPH0562826B2 失效
公开(公告)号：JPH0562826B2
公开(公告)日：1993-09-09
申请号：JP5462885
申请日：1985-03-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , KONDO SHIZUO , KITAMURA YUKINORI , WATABE TOMOYUKI
IPC分类号： H01L27/082 , H01L21/8226 , H01L27/02

6. 发明专利

JPS60186050A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60186050A
公开(公告)日：1985-09-21
申请号：JP1428785
申请日：1985-01-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAYASHI MAKOTO , WATABE TOMOYUKI , OKABE TAKAHIRO , KIMURA MASATOSHI , IMAIZUMI ICHIROU , NAGATA MINORU
IPC分类号： H01L21/8226 , H01L21/331 , H01L27/02 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To coexist a high withstand linear IC and I L circuit by increasing the impurity density of the first semiconductor layer of the I L circuit as compared with the impurity density of other region, thereby reducing the irregularity of betai of the I L even if the irregularity of the thickness of an epitaxial layer is large. CONSTITUTION:A P type separating region 4 having a depth of 0.5mum-several mum is formed, and phosphorus ions of N type impurity are implanted and accumulated in the dosage of 10 -10 cm at the desired position 8 of the I L portion 100 on the surface of an N type layer 3. Then, a collector punching type N type layer 5 is diffused. At this time, a P type separating region 4 and an N type well 8 are simultaneously largely elongated and diffused. Thereafter, P type layers 61, 62, 63 and N type layers 71, 72, 73 are formed by the known semiconductor integrated circuit manufacturing process, metallization is performed, thereby obtaining a desired semiconductor device.

7. 发明专利

JPS61267357A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61267357A
公开(公告)日：1986-11-26
申请号：JP10818885
申请日：1985-05-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKADA YUTAKA , IWASAKI ISAO , WATABE TOMOYUKI
IPC分类号： H01L21/822 , H01L27/04
摘要： PURPOSE:To obtain a semiconductor device having a CR time constant of small dispersion by a method wherein the device is so constructed as to make the values of capacitance and resistance to have negative interrelation to negate dispersion mutually. CONSTITUTION:N-type buried layers 2 are provided at the desired positions on a P-type semiconductor substrate 1, N-type epitaxial layers 3 are formed, and regions isolated electrically according to P-type regions 4 are formed. Then P-type regions 5, 6 are formed at the same time, and by forming an N-type region 7 as to make the part excluding the electrode forming regions of the region 6 on the surface part of the P-type region 6, capacitance is formed at the part whereat the regions 6, 7 are overlapped each other. Namely, capac itances C is formed having relation Cproportional l1, l2. At this time, length l2 is decided at region 7 forming time, while length l1 is decided at region 6 forming time. The resistance value R is in inverse proportion to width W, and because disper sion in terms of DELTAW and DELTAl1 is decided in the same process, dispersion in terms of DELTAW and DELTAl1 is mutually negated partially.

8. 发明专利

JPS60250721A LOGIC CIRCUIT 失效
公开(公告)号：JPS60250721A
公开(公告)日：1985-12-11
申请号：JP10639084
申请日：1984-05-28
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKABE TAKAHIRO , NORISUE KATSUHIRO , HAYASHI MAKOTO , WASHIO KATSUYOSHI , WATABE TOMOYUKI
IPC分类号： H01L27/082 , H01L21/82 , H01L21/8222 , H03K19/00 , H03K19/013 , H03K19/088 , H03K19/177
摘要： PURPOSE:To reduce an area for constituting a three-input NAND circuit and power consumption, to array elements regularly and to make a logic circuit a large-scale integrated circuit by replacing an inverter part of a TTL circuit by an inverted npn transistor (TR). CONSTITUTION:Multi-emitter TRQ1 on the input side of the logic circuit finds out AND of input signals A-C and inputs the AND from its collector to the base of a multi-emitter TRQ2. The operation of the TRQ2 is reversed and the AND of the signals A-C which is outputted from the TRQ1 is inverted and outputted from the collector of the TRQ1. The TRQ2 supplies its collector current determined by its emitter potential VCC and base potential VBE to the base of the TRQ1. Thus, the inverter part of the TTL circuit is constituted of the TRQ2, so that the area of the three-input NAND circuit and its voltage consumption are reduced and the circuit is made a large-scale integrated circuit.

9. 发明专利

JPS60229376A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60229376A
公开(公告)日：1985-11-14
申请号：JP8401884
申请日：1984-04-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： WATABE TOMOYUKI , HAYASHI MAKOTO , HOTSUTA MASAO , WASHIO KATSUYOSHI
IPC分类号： H01L29/866 , H01L29/90
摘要： PURPOSE:To obtain a Zener diode, noises therefrom are low and which has the high degree of integration and a small secular change, by simultaneously using etching for forming an isolation groove as surface etching for shaping the Zener diode and effectively utilizing etching for forming the isolation groove even in an element forming region. CONSTITUTION:A shallow groove 51 is formed at a desired position in the surface of an N type epitaxial layer 3 shaped on a P type semiconductor substrate 1 containing an N type semiconductor layer 2 formed in a desired region on the P type semiconductor substrate 1. A P type semiconductor layer 61 sufficiently reaching up to the N semiconductor layer 2 and an N semiconductor layer 71 are shaped in a region surrounded by a P type semiconductor layer 41 in the shallow groove 51. An anode electrode 8 and a cathode electrode 9 are each formed to the surfaces of the P type semiconductor layer 61 and the N type semiconductor layer 71. In the structure, voltage breakdown is generated in the semiconductor on a crossing line 111 between a diffusion nose section in the upward direction of the N type semiconductor layer 2 and the diffusion nose section of the P type semiconductor layer 61. Accordingly, a Zener diode, noises therefrom are low and which has a small change with time, can be realized.

10. 发明专利

JPS60152052A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60152052A
公开(公告)日：1985-08-10
申请号：JP709784
申请日：1984-01-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAIJIMA MIKIO , OGURA SADAO , KONDOU SHIZUO , WATABE TOMOYUKI , HAYASHI MAKOTO
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082
摘要： PURPOSE:To make each characteristic of an analog element and a digital element to coexist mutually without complicating processes by additionally doping a conductive impurity into a forming region for the digital element selectively. CONSTITUTION:An n type epitaxial layer 12 in comparatively low impurity concentration in an analog element forming region a1 is used as it is, thus forming an npn bipolar transistor Q1. On the other hand, an n type conductive impurity is additionally doped selectively into the n type epitaxial layer 12 in comparatively low concentration in a digital element forming region a2, thus forming an IIL. The effective impurity concentration of the layer 12 in the region a2 is increased relatively because an n type diffusion layer 20 is diffused additionally into the low-concentration n type epitaxial layer 12. Accordingly, each characteristic of an analog element and a digital element can be made to coexist and improved mutually without complicating processes.

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