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1. 发明专利

JP2010161384A BiCDMOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译： BiCDMOS结构及其制造方法
公开(公告)号：JP2010161384A
公开(公告)日：2010-07-22
申请号：JP2010025224
申请日：2010-02-08
申请人： Siliconix Inc , シリコニックス・インコーポレイテッドSiliconix Incorporated
发明人： YILMAZ HAMZA , WILLIAMS RICHARD K , CORNELL MICHAEL E , CHEN JUN WEI
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8222 , H01L21/8228 , H01L21/8234 , H01L21/8238 , H01L21/8248 , H01L27/06 , H01L27/08 , H01L27/082 , H01L27/088 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L29/861
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/0638 , H01L29/0847 , H01L29/0878 , H01L29/1004 , H01L29/42368 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L2924/0002 , Y10S148/009 , Y10S148/085 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a BiCDMOS structure implementing all of a DMOS (doubly diffused metal oxide silicon) power circuit, a CMOS (complementary metal oxide silicon) digital logic circuit and a complementary bipolar analog circuit on a single integrated circuit chip and a method of manufacturing the same. SOLUTION: The BiCDMOS structure includes an embedded insulating region 21B extending downward into a base layer 10, extending upward into an epitaxial layer 40 disposed on the base layer and disposed under an upper main surface of the epitaxial layer, an embedded well region 44B disposed only in the epitaxial layer and extending upward from an upper main surface of the embedded insulating region, and a well region 51B disposed in the epitaxial layer, extending downward from the upper main surface of the epitaxial layer into the epitaxial layer and having a lower main surface in contact with an upper main surface of the embedded well region, wherein a bipolar transistor is formed in the well region and a MOS transistor is formed on an upper main surface part of the epitaxial layer outside the well region. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供实现DMOS（双扩散金属氧化物硅）电源电路，单个集成电路上的CMOS（互补金属氧化物硅）数字逻辑电路和互补双极性模拟电路的BiCDMOS结构芯片及其制造方法。解决方案：BiCDMOS结构包括向下延伸到基底层10中的嵌入式绝缘区域21B，向上延伸到设置在基底层上并设置在外延层的上主表面下方的外延层40中，嵌入阱区域 44B仅设置在外延层中并从嵌入绝缘区的上主表面向上延伸，以及设置在外延层中的阱区51B，其从外延层的上主表面向下延伸到外延层中，并具有下主表面与嵌入阱区的上主表面接触，其中在阱区中形成双极晶体管，并且在阱区外部的外延层的上主表面部分上形成MOS晶体管。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP4117483B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4117483B2
公开(公告)日：2008-07-16
申请号：JP2003560999
申请日：2003-01-15
申请人：サンケン電気株式会社
发明人：昭夫岩渕
IPC分类号： H01L21/8249 , H01L21/266 , H01L21/331 , H01L21/74 , H01L21/761 , H01L21/8222 , H01L21/8234 , H01L21/8248 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8249 , H01L21/266 , H01L21/74 , H01L21/823412 , H01L21/823493 , H01L27/0623

3. 发明专利

JP4074674B2 Method of manufacturing a Dram 失效
公开(公告)号：JP4074674B2
公开(公告)日：2008-04-09
申请号：JP10542596
申请日：1996-04-25
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：李康潤
IPC分类号： H01L21/8242 , H01L23/52 , H01L21/3205 , H01L21/74 , H01L27/108
CPC分类号： H01L21/743 , H01L27/10808 , Y10S257/908

4. 发明专利

JP3850965B2 失效
公开(公告)号：JP3850965B2
公开(公告)日：2006-11-29
申请号：JP32998397
申请日：1997-12-01
IPC分类号： H01L21/265 , H01L21/8238 , H01L21/266 , H01L21/74 , H01L21/761 , H01L27/092

6. 发明专利

JP2006093229A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006093229A
公开(公告)日：2006-04-06
申请号：JP2004273759
申请日：2004-09-21
申请人： Denso Corp , 株式会社デンソー
发明人： KUZUHARA TAKESHI , HIMI KEIMEI , YAMADA AKIRA , NAKAYAMA YOSHIAKI
IPC分类号： H01L21/762 , H01L21/74 , H01L21/76 , H01L27/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is provided with a low-potential reference circuit, a high-potential reference circuit, and a level shifting circuit on the surface layer of an SOI substrate and is secured in the degree of freedom for circuit design, by suppressing the influence of a rapidly changing voltage to the other circuit even if the voltage is applied to one of the circuits.
SOLUTION: In the semiconductor device 100, forming areas of the low-potential reference circuit, the high-potential reference circuit, and the level shifting circuit are insulated and separated from one another by a first trench 4 formed to reach an embedded oxidized film 3, and a first impurity layer 1a having the same conductivity type as that of a first semiconductor layer 1 and a impurity concentration higher than that of the layer 1 is formed on the embedded oxidized layer 3 in the first semiconductor layer 1. In addition, a second embedded oxidized layer 3a is formed in the first semiconductor layer 1 in the forming area of at least one of the low-potential reference circuit, the high-potential reference circuit, and the level shifting circuit.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供在SOI衬底的表面层上设置有低电位参考电路，高电位参考电路和电平移位电路的半导体器件，并且被确定为通过抑制对另一个电路的快速变化的电压的影响，即使将电压施加到电路中的一个电路，也可以实现电路设计的自由度。解决方案：在半导体器件100中，形成低电位参考电路，高电位参考电路和电平移位电路的区域通过形成为达到嵌入的第一沟槽4彼此绝缘和分离在第一半导体层1的嵌入的氧化层3上形成有与第一半导体层1的导电类型相同的导电类型的第一杂质层1a和高于层1的杂质浓度的第一杂质层1a。此外，在低电位基准电路，高电位基准电路和电平移位电路中的至少一个的形成区域中的第一半导体层1中形成第二嵌入式氧化层3a。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005530347A Improved structure and method for locally embedded interconnection 审中-公开
公开(公告)号：JP2005530347A
公开(公告)日：2005-10-06
申请号：JP2004514138
申请日：2002-06-14
申请人：インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人：ウォン、ロバート、シー , グレシェンコフ、オレグ , ディヴァカルニ、ラーマチャンドラ , マンデルマン、ジャック、エイ , ラデンス、カール、ジェイ
IPC分类号： H01L29/41 , H01L21/3205 , H01L21/74 , H01L21/76 , H01L21/762 , H01L21/768 , H01L21/82 , H01L21/8234 , H01L21/84 , H01L23/52 , H01L23/535 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L21/743 , H01L21/76895 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/42384 , H01L29/7839 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要：【課題】基板の単結晶半導体層内に集積回路の埋め込み相互接続を形成するための構造および方法を提供すること。
【解決手段】埋め込み相互接続は、堆積された導体から形成され、単結晶半導体層内に形成された電子デバイスの単結晶領域と接触する１つまたは複数の垂直側壁を備える。

8. 发明专利

JP2005251973A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005251973A
公开(公告)日：2005-09-15
申请号：JP2004060210
申请日：2004-03-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： INOUE YASUTAKE , OTA HIROYUKI
IPC分类号： H01L21/76 , H01L21/31 , H01L21/74 , H01L21/762 , H01L27/08 , H01L29/78 , H01L31/113
CPC分类号： H01L21/76232 , H01L21/31053 , H01L21/31111 , H01L21/823878 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device using an STI of excellent transistor characteristics.
SOLUTION: The manufacturing method of a semiconductor device comprises (a) a process of forming a stopper layer of Chemical Mechanical Polishing on a semiconductor substrate surface; (b) a process of forming a device separation trench in the stopper layer and in the semiconductor substrate; (c) a process of depositing a nitride film so as to cover a surface in the trench; (d) a process of depositing a first oxide film using high density plasma oxidation so as to embed at least a lower portion of the trench on which the nitride film is deposited; (e) a process of washing out the first oxide film on the trench side wall with dilute hydrofluoric acid, and leaving the nitride film behind by at least a part of the thickness thereof; (f) a process of depositing a second oxide film with high density plasma oxidation so as to embed the trench after washed out; and (g) a process of removing the oxide film on the stopper layer with Chemical Mechanical Polishing.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供使用具有优异晶体管特性的STI的半导体器件的制造方法。解决方案：半导体器件的制造方法包括（a）在半导体衬底表面上形成化学机械抛光的阻挡层的工艺; （b）在阻挡层和半导体衬底中形成器件分离沟槽的工艺; （c）沉积氮化物膜以覆盖沟槽中的表面的工艺; （d）使用高密度等离子体氧化沉积第一氧化膜以便嵌入沉积有氮化物膜的沟槽的至少下部的工艺; （e）用稀氢氟酸在沟槽侧壁上冲洗出第一氧化膜并使氮化膜留在其厚度的至少一部分上的过程; （f）沉积具有高密度等离子体氧化的第二氧化物膜的工艺，以便在冲洗后嵌入沟槽; 和（g）用化学机械抛光去除阻挡层上的氧化膜的工艺。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005508568A The formation of the front side contact of silicon-on-insulator substrate 审中-公开
公开(公告)号：JP2005508568A
公开(公告)日：2005-03-31
申请号：JP2002572618
申请日：2002-03-12
申请人：ハネウェル・インターナショナル・インコーポレーテッド
发明人：フェチナー，ポール・エス , ユエ，チェイサン
IPC分类号： H01L21/28 , H01L21/74 , H01L21/762 , H01L21/768 , H01L23/52 , H01L23/522 , H01L27/12
CPC分类号： H01L21/743 , H01L21/7624
摘要：シリコン・オン・インシュレータ（ＳＯＩ）ウェーハに表側コンタクトを形成する方法が説明される。接続多結晶シリコンがシリコン基板層をコンタクト用プラグに接続する。この接続はＳＯＩウェーハの底部基板を接地する又は底部基板にバイアスをかける手段を提供する。ドーピングを追加するためにスペーサを加えることができる。

10. 发明专利

JP3575908B2 Semiconductor device 失效
公开(公告)号：JP3575908B2
公开(公告)日：2004-10-13
申请号：JP7422596
申请日：1996-03-28
申请人：株式会社東芝
发明人：幸一遠藤 , 洋介高木
IPC分类号： H01L21/762 , H01L21/74 , H01L21/761 , H01L27/12 , H01L29/73 , H01L29/739 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7824 , H01L21/743 , H01L27/1203 , H01L29/7317 , H01L29/7394

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