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1. 发明专利

JPS6015960A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6015960A
公开(公告)日：1985-01-26
申请号：JP12324483
申请日：1983-07-08
申请人： HITACHI LTD
发明人： YAMAZAKI KOUICHI , OKADA YUTAKA , KANEKO KENJI , OKABE TAKAHIRO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H01L27/02
摘要： PURPOSE:To reduce the scattering of a CR value in a CR time constant circuit by providing the CR time constant circuit constituted by a resistor R formed by polycrystalline silicon and a capacitance C formed by polycrystalline silicon, an oxide film and a metallic electrode. CONSTITUTION:An oxide film 10 is shaped on a semiconductor substrate 1, and a polycrystalline silicon layer 20 in thickness H is deposited. The polycrystalline silicon 20 is patterned. An impurity is doped to a section as one electrode of a capacitance and a contact section in a resistor through polycrystalline silicon ion implantation, etc. to form polycrystalline silicon 21 having low resistance. Polycrystalline silicon is oxidized in order to form a protective film consisting of polycrystalline silicon and an oxide film as a dielectric for the capacitance to shape oxide films 30 in thickness d. The thickness H' of polycrystalline silicon is brought to approximately H'=H-d/2 at that time. The oxide films are removed selectively in order to make contacts, and metallic electrodes 40 are formed, thus completing the semiconductor device.

2. 发明专利

JPS605552A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS605552A
公开(公告)日：1985-01-12
申请号：JP11272983
申请日：1983-06-24
申请人： HITACHI LTD
发明人： YAMAZAKI KOUICHI , OKADA YUTAKA , KANEKO KENJI , WATABE TOMOYUKI , OKABE TAKAHIRO
IPC分类号： H01L21/8226 , H01L21/331 , H01L27/082 , H01L29/72 , H01L29/73 , H01L29/732 , H01L27/08
摘要： PURPOSE:To reduce the collector or emitter position dependency by forming a half of an emitter diffused region coupled to an emitter or a collector electrode with the first side of a base region and the residue with the second side opposed to the first side in walled structures, and forming the both diffused layers with the residual three sides in non-walled structure. CONSTITUTION:The first emitter diffused layer 5 which becomes a walled structure only with the first side of a base region established with an oxidized film 3, and the second emitter diffused layer 5' which becomes a walled structure only with the second side opposed to the first side of the base region are provided, and connected via an electrode 6. One side of the emitter diffused layer is in a walled structure, and the other side is formed in non-walled structure, and since a space is formed between the layers 5 and 5', the sheet resistance of this part can be reduced, and a parasitic base series resistance can be reduced. Since the layers 5, 5' are connected via an electrode, the emitter area observed from the electrode can be, even if masks are displaced, always maintained constant.

3. 发明专利

JPS5911644A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5911644A
公开(公告)日：1984-01-21
申请号：JP11994782
申请日：1982-07-12
申请人： Hitachi Ltd
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/8226 , H01L21/331 , H01L21/76 , H01L21/762 , H01L27/082 , H01L29/73 , H01L29/78
CPC分类号： H01L21/76202
摘要： PURPOSE:To form a high density impurity region at the desired position on the circumferential part of an active area by a method wherein impurities are doped at the prescribed position on a semiconductor region by performing a self-alignment method using a mask material pattern as a mask, and a thick oxide film region is formed by performing a selective oxidation. CONSTITUTION:A P type region 13 can be formed on the circumference of the region which will be turned to the active area of a transistor when a thick oxide film 10 is formed at the part which is not covered by a nitride film 102 when an oxidation is performed. A P type base region 4 is formed by removing the nitride film 102. Besides, after an oxide film 11 has been deposited, an emitter region 5 is formed, and metal electrodes 7 and 8 for base and emitter are formed. As the region 13 is formed by performing a self-matching method, no increase is made in transistor area, thereby producing an excellent effect in a high degree. Besides, the impurities on the circumference of the base region 4 can be formed in high density by having the region 13.
摘要翻译：目的：通过使用掩模材料图案作为自对准方法进行自对准方法，通过在半导体区域上的规定位置掺杂杂质的方法，在有源区的圆周部分的期望位置处形成高密度杂质区域掩模，并且通过进行选择性氧化形成厚的氧化膜区域。构成：当氧化为氧化膜时，在未被氮化物膜102覆盖的部分形成厚氧化膜10时，AP型区域13可以形成在将被转向晶体管的有源区域的区域的圆周上执行。通过去除氮化物膜102来形成P型基区4.此外，在沉积氧化物膜11之后，形成发射区5，形成用于基极和发射极的金属电极7和8。由于通过执行自匹配方法形成区域13，所以在晶体管区域中不会增加，从而在高度上产生优异的效果。此外，通过具有区域13，可以高密度地形成基底区域4的圆周上的杂质。

4. 发明专利

JPS5989457A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5989457A
公开(公告)日：1984-05-23
申请号：JP19891882
申请日：1982-11-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAZAKI KOUICHI , OKADA YUTAKA , KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/72
摘要： PURPOSE:To improve an insulation between a polycrystalline silicon layer and a metallic electrode, and to prevent a short circuit by forming an oxidation- resisting film to the upper section of polycrystalline silicon, independently oxidizing only a side wall section and thickly forming only the oxide film on the side wall section of the polycrystalline silicon. CONSTITUTION:A high-concentration N type region 2, a P type region 3 as a channel stopper, an N type epitaxial layer 4, an isolation oxide film 5, a high- concentration N type region 6 for extracting a collector and a P type region 7 as a base region are formed on a P type semiconductor substrate 1. A polycrystalline silicon layer 8 as a region for extracting an emitter, an oxide film 9 and a nitride film 10 are formed. The nitride film 10, the oxide film 9 and the silicon 8 are patterned, and an emitter electrode and a collector electrode are formed. An oxide film 11 is formed through oxidation, an emitter region 12 is formed through heat treatment, and the base region 7 is exposed. The film thickness of an upper section and a side section can be controlled because the oxide film 9 and 11 can be formed through separate processes.

5. 发明专利

JPS58204564A Manufacture of thin film capacity 失效
标题翻译：薄膜电容的制造
公开(公告)号：JPS58204564A
公开(公告)日：1983-11-29
申请号：JP8662182
申请日：1982-05-24
申请人： Hitachi Ltd
发明人： YAMAZAKI KOUICHI , KANEKO KENJI , OKADA YUTAKA , OKABE TAKAHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/822 , H01L27/04 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0688
摘要： PURPOSE:To provide a thin film capacity of high accuracy on a field oxidized film by forming one electrode of the capacity and a thin dielectric film during coexistent steps of manufacturing a semiconductor and preventing the variation in the shape during the steps. CONSTITUTION:A thick oxidized film 2, the gate of an MOSFET and polysilicons 3, 4 to become one electrode of a thin film capacity are formed on an N type Si substrate 1, and the layer 4 is completely covered with an Si3N4 film 5. When P type layers 6, 7 are formed and oxidized, the shape of the layer 3 is altered, but the shape of the layer 4 is not varied due to the film 5, and the thickness of the film 5 does not change. Subsequently, electrodes 8-10 are attached to complete it. According to this configuration, a capacity of high accuracy can be obtained under good controllability, and no influence is affected by the coexistent FETs.
摘要翻译：目的：通过在制造半导体的共同步骤中形成一个容量的电极和薄的电介质膜，并在步骤中防止形状的变化，在场氧化膜上提供高精度的薄膜容量。构成：在N型Si衬底1上形成厚氧化膜2，MOSFET的栅极和成为薄膜电容的一个电极的多晶硅3,4，并且层4被Si 3 N 4膜5完全覆盖。当P型层6,7形成并被氧化时，层3的形状被改变，但是层4的形状由于膜5而没有变化，并且膜5的厚度没有变化。随后，附接电极8-10以完成它。根据该结构，能够在良好的控制性的情况下获得高精度的容量，不会对共存的FET产生影响。

6. 发明专利

JPS6060765A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6060765A
公开(公告)日：1985-04-08
申请号：JP16817183
申请日：1983-09-14
申请人： HITACHI LTD
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/76 , H01L21/8249 , H01L27/06 , H01L29/78
摘要： PURPOSE:To reduce parasitic capacitance and parasitic resistance, and to enable operation at high speed by thinning an oxide film on a section as a contact for a source of a drain in an MOS integrated circuit. CONSTITUTION:An oxide film 5 and a non-oxidizable film 6 are formed on a substrate 100, and oxidized while leaving the film 6 in a desired section to shape a thick oxide film 7. A polycrystalline silicon layer 15 is formed to an opening section 12 shaped by etching the film 6, and impurity ions are implanted to form a source region 18 and a drain region 19. An oxide film 20 is formed through oxidation, the non-oxidizable film 6 is removed and the thin oxide film 5 is also removed, and contact holes 24, 25 for a source and a drain are shaped. Lastly, electrodes 27, 28 are formed.

7. 发明专利

JPS5979566A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5979566A
公开(公告)日：1984-05-08
申请号：JP18904982
申请日：1982-10-29
申请人： Hitachi Ltd
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L29/417 , H01L29/73
CPC分类号： H01L29/41708
摘要： PURPOSE:To narrow the interval between emitter, base electrode windows, to reduce the area, and to enhance the frequency characteristic of a semiconductor device by a method wherein the base terminals of the vertical transistor are led out according to poly-Si layers. CONSTITUTION:An N type epitaxial layer 52 on a P type Si substrate 50 buried with an N type layer 51 is isolated by P type layers 53 and field oxide films 54, and a P type layer 2 is provided. An SiO2 film 60 and an Si3N4 film 61 are accumulated, windows are opened, N type poly-Si layers 90 added with P are provided selectively, and the surfaces thereof are covered with SiO2 film 55. Windows are opened in the films 60, 61, P ions are implanted covering the collector electrode windows with a resist to provide an N type base 3, then a P type emitter 4 and P type collector lead out layers 10 are provided, and a heat treatment is performed to connect base lead out layers 5 to the N type base 3. Electrodes 6, 7 are equipped finally. According to this construction, the distances between the emitter electrode 6 and the base electrodes 7 of the vertical transistor can be made to 2mum or less to be reduced to 1/4 of usual, the element can be formed in a small type, junction capacity reduced, and the frequency characteristic is improved.
摘要翻译：目的：通过以垂直晶体管的基极端子根据多晶Si层引出的方法，缩小发射极，基极窗口之间的间隔，减小面积，并提高半导体器件的频率特性。构成：通过P型层53和场氧化膜54隔离在N +型层51上埋设的P型Si衬底50上的N型外延层52，并提供P型层2。堆积SiO 2膜60和Si 3 N 4膜61，打开窗口，选择性地提供添加有P的N +型多晶硅层90，并且其表面被SiO 2膜55覆盖。窗口在膜中打开 60,61，用抗蚀剂注入覆盖集电极窗口的P离子以提供N型基体3，然后提供P +型发射体4和P +型集电极引出层10，并且加热执行处理以将基底引出层5连接到N型基底3.电极6,7最终装备。根据这种结构，垂直晶体管的发射极电极6和基极电极7之间的距离可以为2μm或更小，以减小到通常的1/4，元件可以形成为小型的结电容降低，频率特性提高。

8. 发明专利

JPS6060760A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6060760A
公开(公告)日：1985-04-08
申请号：JP16817283
申请日：1983-09-14
申请人： HITACHI LTD
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/74 , H01L21/331 , H01L21/8226 , H01L27/082 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To increase withstanding voltage and reduce collector series resistance by omitting an N layer just under a base while forming an N buried layer just under at least one part of the periphery of a base layer in a bipolar transistor. CONSTITUTION:An N type epitaxial layer 3 and an N type region 10 are formed on a semiconductor substrate 1, the layer 3 and region 10 are used as collector regions while a P type base region 6 is shaped in the region 3, and an N type emitter region 9 is formed in the base region 6, thus constituting a bipolar transistor. In the transistor constituted in this manner, an N buried layer 2 is shaped just under the periphery of the base layer 6, and is not formed just under the base layer 6. Accordingly, the transistor having high withstanding voltage can be formed on the thin epitaxial layer. Collector resistance can be reduced.

9. 发明专利

JPS6020534A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6020534A
公开(公告)日：1985-02-01
申请号：JP12767583
申请日：1983-07-15
申请人： HITACHI LTD
发明人： YAMAZAKI KOUICHI , OKADA YUTAKA , KANEKO KENJI , OKABE TAKAHIRO
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To perform the microminiaturization of an element and the lowering of the resistance of a wiring compatible by doping arsenic to polycrystalline silicon on an emitter in a transistor and doping either of arsenic and phosphorus or only phosphorus to polycrystalline silicon for the wiring except a section on the emitter through a self-alignment method. CONSTITUTION:A polycrystalline silicon layer 8 is formed in such a manner that non-doped polycrystalline silicon is deposited and arsenic is doped through the implantation of arsenic or polycrystalline silicon to which arsenic is doped is used. Phosphorus is diffused to the polycrystalline silicon 8 from phosphorus glass 21 through heat treatment, phosphorus is doped to the polycrystalline silicon, and polycrystalline silicon layers 8' to which phosphorus is doped are formed. Phosphorus is not doped to an emitter and the polycrystalline silicon on collector withdrawal regions 6, 7 at that time, phosphorus is not doped to an emitter region, and phosphorus can be doped to the polycrystalline silicon except a section on the emitter region in a self-alignment manner. The polycrystalline silicon is patterned, a protective oxide film 10 is shaped, and a base metallic electrode 9 is formed, thus forming a transistor.

10. 发明专利

JPS5989454A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5989454A
公开(公告)日：1984-05-23
申请号：JP19891682
申请日：1982-11-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKADA YUTAKA , KANEKO KENJI , OKABE TAKAHIRO , NAGATA MINORU , YAMAZAKI KOUICHI , MATSUMOTO KEIZOU
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L29/73 , H03K19/091
摘要： PURPOSE:To reduce delay time for the transmission of signals in a laminated I L by using a current mirror system in order to rapidly extinguish stored charges in a transistor (Tr). CONSTITUTION:A power supply 1, an injector 2 and a common emitter 3 are set up to an upper-layer I L circuit block A. The injector line 3 and a common emitter 4 are set up to a lower-layer I L circuit block B. Q0 represents the N-P-N Tr of an I L gate, and Q2 represents an N-P-N Tr constituting the interface of the laminated I L. Q3 and Q4 constitute a current mirror circuit. A period while Q3 is turned OFF is shortened because the base currents are small and stored charges are little.

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