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1. 发明专利

JPS6012757A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6012757A
公开(公告)日：1985-01-23
申请号：JP11834583
申请日：1983-07-01
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/8226 , H01L27/082 , H03K19/018 , H03K19/091 , H01L27/08 , H03K19/00
摘要： PURPOSE:To make the operation stable and highly accurate by a method wherein the collector-base coupling or the drain-gate coupling of transistors determining constant current is connected to the collector or drain of the other transistor pair for constant current generation having polarity different from that of said pair, in the IC with an I L circuit incorporated in the emitter or source side of the transistor pair constituting a constant current circuit. CONSTITUTION:The other pair of constant current transistors Q3 and Q4 having the polarity inverse to that of the following pair are connected to the pair of constant current transistors Q1 and Q2 with the I L circuit incorporated, and the collector of Q3 is connected to that of Q1. The output current of Q2 is determined by the transistor Q4 and a resistor RB1 in such a manner. This circuit allows the potential of a point A to vary with the action of the circuit 10. Even when the potential of a point B varies according to it, the variation of the value of current flowing through Q1 and Q2 becomes completely eliminated because of the high impedance of Q3 on the collector side from the point B.

2. 发明专利

JPS60185290A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS60185290A
公开(公告)日：1985-09-20
申请号：JP3037585
申请日：1985-02-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MATSUMOTO KEIZOU , KANEKO KENJI , OKABE TAKAHIRO
IPC分类号： G11C11/414 , G11C11/34
摘要： PURPOSE:To stabilize writing and to expand a writing range by making word line current at a selecting time and writing current proportional to the current amplification factor of information writing/reading TR in a semiconductor storage device using an I L element. CONSTITUTION:A memory Cell forming an FF consisting of the I L element including writing/reading N type TRs N8, N9 are connected to peripheral circuits consisting of N type TRs N1, N2, N3 and N5 respectively and to be used for cell current IW at a selecting time, word line current IW at a selecting time and writing current IW. The current amplification factor of the TRs N1, N2, N4, N5 is proportional to the current amplification factor hFE of the TRs N8, N9 and the current IW , IW , IW is proportional to the amplification factor hFE. Therefore, the current IW is made proportional to the IW and the writing operation range is increased. Since the current IW is also proportional to the IW , the word line W is prevented from the reduction of potential. Since the condition of IW>1/2hFEXIW is satisfied even if the amplification factor hFE is dispersed, stable writing is executed.

3. 发明专利

JPS5989454A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5989454A
公开(公告)日：1984-05-23
申请号：JP19891682
申请日：1982-11-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKADA YUTAKA , KANEKO KENJI , OKABE TAKAHIRO , NAGATA MINORU , YAMAZAKI KOUICHI , MATSUMOTO KEIZOU
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L29/73 , H03K19/091
摘要： PURPOSE:To reduce delay time for the transmission of signals in a laminated I L by using a current mirror system in order to rapidly extinguish stored charges in a transistor (Tr). CONSTITUTION:A power supply 1, an injector 2 and a common emitter 3 are set up to an upper-layer I L circuit block A. The injector line 3 and a common emitter 4 are set up to a lower-layer I L circuit block B. Q0 represents the N-P-N Tr of an I L gate, and Q2 represents an N-P-N Tr constituting the interface of the laminated I L. Q3 and Q4 constitute a current mirror circuit. A period while Q3 is turned OFF is shortened because the base currents are small and stored charges are little.

4. 发明专利

JPS63100763A INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63100763A
公开(公告)日：1988-05-02
申请号：JP24529686
申请日：1986-10-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG , HITACHI MAXELL
发明人： NAKAGAWA TETSUYA , KANEKO KENJI , HAGIWARA YOSHIMUNE , KIUCHI ATSUSHI , SUZUKI NORIYASU , TOYOMASU TAKANO , TAKAMORI HIROSHI , KISHI KAZUMASA
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To lead out arbitrary input/output terminals to input terminals for a VLSI in a selected order by forming a peripheral bus along the outer circumference of a VLSI chip among input/output terminals and a plurality of sub-LSIs. CONSTITUTION:Subchips in the number of k of a VLSI chip 100 constituted of sub-LSIs 104-107 have n1-nk input/output signals respectively, and some of them are connected by an internal bus 103 through the interfaces. The chip 100 has a bus 102 going around the chip 100 among input/output devices 101 and the chips 104-107. The bus 102 is connected to all or one part of input/ output signals for the chips 1-k, and connected to pads or the devices 101 through a selector. Input/output signals for arbitrary subchips can be led out to the pads in a selected order by using the bus 102.

5. 发明专利

JPS62146008A SELECTING CIRCUIT 失效
公开(公告)号：JPS62146008A
公开(公告)日：1987-06-30
申请号：JP28819585
申请日：1985-12-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： KIUCHI ATSUSHI , ISHIDA JUN , KANEKO KENJI , NAKAGAWA TETSUYA , SATOU TOMORU , MASUMURA SHIGEKI , SUZUKI NORIYASU , HAGIWARA YOSHIMUNE
IPC分类号： H03K17/00 , H03K17/693
摘要： PURPOSE:To make a quick operation possible by selecting one signal in each period from (n-1)-number of input signals taken in from the external and one input signal, which is obtained by feeding back the output of the preceding period, to make it unnecessary to set the time when a decoding signal for control is settled. CONSTITUTION:(n-1)-Number of input signals out of n-number of input signals to be selected are input signals from the external, and remainder one is the signal obtained by feeding back the output of a selecting circuit 409 or a logic circuit 406 following the circuit 409. These n-number of input signals are controlled by a control signal C410 for selection. If any of (n-1)-number of external input signals is not selected, the control signal C410 selects certainly the feedback signal of the state in the preceding period. This feedback signal is selected then to eliminate the no-selection mode, and thereby, the output of the selecting circuit 409 is certainly outputted in each period. Thus, a preceding erroneous selecting signal is cancelled immediately with a correct selecting signal even if the erroneous signal is temporarily selected in the initials stage of synchronization.

6. 发明专利

JPS5875867A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5875867A
公开(公告)日：1983-05-07
申请号：JP17300981
申请日：1981-10-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： G11C11/416 , H01L21/8226 , H01L21/8229 , H01L27/082 , H01L27/102 , H03K19/086
摘要： PURPOSE:To highly integrate a semiconductor device by commonly using components of a sense amplifier with a plurality of bits and commonly using an element isolating region with a plurality of elements. CONSTITUTION:The structure of a sense amplifier is composed of a plurality of bit units, each bit voltage sensing circuit has only a constant-current circuit (TrP1 and N1, P2 and N2, P3 and N3 are I L current mirror circuits) controlled in the current with differential pairs (N-P-N transistors TrT3-T6) and a control signal, and the loads TrT1, T2 of the differential circuit except this and level shifting circuit are commonly used with the plural bits. The TrT1, T2 are common at the bases and are the same potential as the collectors of TrT4, T6, and accordingly, can be similarly disposed, and the current mirror circuit can be similarly disposed at the same isolating region.

7. 发明专利

JPS6012823A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6012823A
公开(公告)日：1985-01-23
申请号：JP11834683
申请日：1983-07-01
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/8226 , H01L27/082 , H03K19/00 , H03K19/003 , H01L27/08
摘要： PURPOSE:To remove interference between analog circuits when I L circuits are incorporated in a high voltage circuit and to actuate the titled circuit stably and highly accurately by collecting each block of an analog circuit and supplying current normalized in respective blocks to respective I L circuits. CONSTITUTION:The analog circuit is divided into blocks A, B and current is supplied to respective I L circuit blocks 10, 10'. Consequently, noises on the earth sides which are generated in the respective analog circuits A, B are absorbed by the respective I L circuits 10, 10' and are not transmitted to the other analog circuit. Thus, signal interference between the circuits A and B can be prevented.

8. 发明专利

JPS5989457A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5989457A
公开(公告)日：1984-05-23
申请号：JP19891882
申请日：1982-11-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAZAKI KOUICHI , OKADA YUTAKA , KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/72
摘要： PURPOSE:To improve an insulation between a polycrystalline silicon layer and a metallic electrode, and to prevent a short circuit by forming an oxidation- resisting film to the upper section of polycrystalline silicon, independently oxidizing only a side wall section and thickly forming only the oxide film on the side wall section of the polycrystalline silicon. CONSTITUTION:A high-concentration N type region 2, a P type region 3 as a channel stopper, an N type epitaxial layer 4, an isolation oxide film 5, a high- concentration N type region 6 for extracting a collector and a P type region 7 as a base region are formed on a P type semiconductor substrate 1. A polycrystalline silicon layer 8 as a region for extracting an emitter, an oxide film 9 and a nitride film 10 are formed. The nitride film 10, the oxide film 9 and the silicon 8 are patterned, and an emitter electrode and a collector electrode are formed. An oxide film 11 is formed through oxidation, an emitter region 12 is formed through heat treatment, and the base region 7 is exposed. The film thickness of an upper section and a side section can be controlled because the oxide film 9 and 11 can be formed through separate processes.

9. 发明专利

JPS58169393A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS58169393A
公开(公告)日：1983-10-05
申请号：JP5166982
申请日：1982-03-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO
IPC分类号： G11C11/414 , G11C11/416
摘要： PURPOSE:To execute read-out at a high speed, by connecting a bit line to a constant-voltage source through a resistance, and operating write/read-out transistor (TR) of a storage cell in the reverse direction at the time of read-out. CONSTITUTION:A titled device is constituted by providing a pull-up resistance RB and an NPN TRN6. Pull-up potential VP is higher than potential of a word line V , therefore, when write/read-out TRSN3, N4 of a storage cell are operated in the reverse direction, the TRsN3, N4 absorb a current from bit lines B0, B1. Magnitude of this current becomes IS/IUS times of a storage cell being in a nonselecting state, in case of a storage cell being in a selecting state. Accordingly, when the current IS is taken sufficiently larger than IUS, contents of the cell being in a selecting state can be read out as a potential difference of the bit lines B0, B1, even in case when a lot of cells being in a nonselecting state are connected to the same bit lines B0, B1.

10. 发明专利

JPH10112646A SEMICONDUCTOR LOGIC CIRCUIT 失效
公开(公告)号：JPH10112646A
公开(公告)日：1998-04-28
申请号：JP26406396
申请日：1996-10-04
申请人： HITACHI LTD
发明人： NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , KANEKO KENJI , KUSUNOKI TAKESHI , SAITO KAYOKO , USAMI MASAMI , YAMAGUCHI KUNIHIKO
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/003 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To prevent malfunction by restoring an output node to a normal level after noise disappears even when the noise is generated in an input signal and the output node is discharged in error. SOLUTION: Supposing that input signals INO-INn are in an N-channel logic block NBL with ϕ=1 (decision phase), then an output node OUT precharged to a VDD should stay in the VDD without being discharged in a pre-charge phase. However, in the case that noise intrudes in the input signals INO-INn and the logic block NBL is generated even momentarily, the output node is discharged to a power supply VSS. However, when the noise disappears and the NBL is restored to a nonconductive state, conversely the n-channel logic block/NBL is made conductive. Thus, an output node/OUT is discharged to the VSS and a feedback transistor(TR) MP3 is made conductive. Thus, the discharged output node OUT is charged by the MP3 and restored again to a normal level (VDD).

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