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    • 4. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS5996762A
    • 1984-06-04
    • JP20607582
    • 1982-11-26
    • HITACHI LTDHITACHI MICROCUMPUTER ENG
    • WASHIO KATSUYOSHIHAYASHI MAKOTOWATABE TOMOYUKIOKABE TAKAHIRONAGATA MINORU
    • H01L27/04H01L21/822H01L29/94
    • PURPOSE:To enable to increase the capacitance of a capacitance element without increasing the number of processes by providing a plurality of grooves of the same depth as that of a groove for forming an island region on the surface of each capacitor element at the same with the formation of the island region. CONSTITUTION:A system wherein grooves 100 formed by etching in N type epitaxial layer 2 and P type impurity regions 4 are both used is used for isolating elements. A plurality of grooves 200 having the same depth as the etched groove 100 used for the element isolation are formed on the surface of each capacitance element at the same time with the formation of the grooves 100, an insulation film 3 is formed thereon, and further an electrode 6 is formed thereon, resulting in the formation of an MOS capacitor structure by means of the electrode 6, the insulation film 3, and the P type impurity region 5. An electrode 7 provided by penetrating through the insulation film 3 conducts with the P type impurity region 5. The MOS capacitor having this structure can utilize also the area of the side wall surface of the groove 200 formed on the surface of the capacitor element as a charge accumulation area, therefore the capacitor increases by the increment of this side wall area.