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1. 发明专利

JP2003046532A Facility-monitoring system, facility-monitoring terminal, local monitoring device, remote monitoring device, and computer software 审中-公开
标题翻译：设备监控系统，设备监控终端，本地监控设备，远程监控设备和计算机软件
公开(公告)号：JP2003046532A
公开(公告)日：2003-02-14
申请号：JP2001228267
申请日：2001-07-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KASAMATSU OSAMU , FUJIWARA KATSUHIRO , SAKAI KUNIYOSHI
IPC分类号： H04L12/46
摘要： PROBLEM TO BE SOLVED: To provide an economical and efficient facility-monitoring system by organic coordination among a facility/device user, a maintenance service personnel in charge, and a facility/device manufacture by managing a maintenance manual, maintenance component information, daily/periodic inspection recordings and maintenance history or the like unitarily with automatic collection data.
SOLUTION: In the facility-monitoring system comprising the facility-monitoring terminal 2, a local monitoring device 3 and a remote monitoring device 4, the facility monitoring terminal 2 includes an input conversion function 21 for an analog signal, a pulse signal and a contact signal or the like, a signal-processing arithmetic function 22, a processing/arithmetic result recording storage function 24, an external information input function 23 from an external input device 11, and a data/information/signal transmission reception function 25; the local monitoring device 3 has a data/information/signal transmission reception function; and the remote monitoring device 4 includes a facility/device monitoring/maintenance management information storage function; and a data/information/signal transmission reception function with external devices 51, 52 and the local monitoring device 3.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过管理维护手册，维护部件信息，日常/机器设备，通过设备/设备用户，维护维护人员和设备/设备制造之间的有机协调来提供经济和有效的设备监控系统，定期检查记录和维护历史等与自动收集数据一体。解决方案：在设备监控终端2，本地监控设备3和远程监控设备4的设备监控系统中，设备监控终端2包括用于模拟信号，脉冲信号和联系人的输入转换功能21 信号处理算术功能22，处理/算术结果记录存储功能24，来自外部输入装置11的外部信息输入功能23以及数据/信息/信号发送接收功能25; 本地监视装置3具有数据/信息/信号发送接收功能; 并且远程监视装置4包括设备/设备监视/维护管理信息存储功能; 以及具有外部设备51,52和本地监视设备3的数据/信息/信号发送接收功能。

2. 发明专利

JPH05197405A PROGRAMMABLE CONTROLLER WITH AUTOMATIC ACCESS FUNCTION FOR TELEPHONE LINE 失效
公开(公告)号：JPH05197405A
公开(公告)日：1993-08-06
申请号：JP1007292
申请日：1992-01-23
申请人： HITACHI LTD
发明人： TAMURA FUMIYUKI , FUJIWARA KATSUHIRO , SANO MASAHIRO , FURUSAWA SHINGO
IPC分类号： G05B19/05 , H04M11/00
摘要： PURPOSE:To facilitate the generation of a user program including communication control with a personal computer through the use of a public line by providing a public line interface part for a public communication network and transmitting/receiving information in accordance with a private communication instruction written into a sequence program. CONSTITUTION:When the address of a program memory in a user memory 3 is instructed by a program step which a program counter 2 shows, and the sequence program of the corresponding step is read, an instruction code in the program is inputted to a CPU 1, and it is decoded and executed in the CPU 1. A part except for the instruction code is inputted to an input/output interface part 4 or the user memory 3 as an operand. A state value or data is read from the input of a designated number, and it is transferred to an interface part 6 or data is received from the public line interface part 6. The state value is written into designated output and is written into the user memory 3 so as to execute sequence control.

3. 发明专利

JPH04107704A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPH04107704A
公开(公告)日：1992-04-09
申请号：JP22746890
申请日：1990-08-29
申请人： HITACHI LTD
发明人： SHIKAYAMA MASAHIRO , MOROOKA YASUO , OSHIGA TAKAYUKI , FUJIWARA KATSUHIRO
IPC分类号： G05B19/05
摘要： PURPOSE:To average the execution timing of each control loop and to uniformalize the response delay of sequence control by discriminating the execution timing of each loop under a condition that the number of continuous system control loops executed in a designated cycle can be minimized when the control of the continuous system control loop is executed. CONSTITUTION:The area length of a scheduling table 201 is set in accordance with the least common multiple of a ratio of timer inter-ruption cycle that is the generating cycle of an execution cycle to a sampling cycle that is the execution cycle of each PID loop. Data of loop number is stored in areas 1-m corresponding to the generating timing of timer interruption as the data to specify a PID control loop set under the condition that the number of PID loops executed in the generating cycle of the timer interruption is minimized. Thereby, it is possible to uniformalize the response delay of the sequence control.

4. 发明专利

JPS62145329A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS62145329A
公开(公告)日：1987-06-29
申请号：JP28550285
申请日：1985-12-20
申请人： HITACHI LTD
发明人： FUJIWARA KATSUHIRO , OSHIGA TAKAYUKI , KASAHARA TOSHIRO , ITO ATSUSHI
IPC分类号： G06F9/48 , G05B19/05 , G06F9/46
摘要： PURPOSE:To operate a whole control system without any contradiction even when a process interruption is inputted in an optional state by setting a specific instruction which identifies the start of a relay sequence circuit and permitting the process interruption only when the instruction is read out. CONSTITUTION:When an interruption request is inputted from a process, a flip-flop 61 is set and when a signal which indicates a relay sequence head circuit is inputted from a control line (c) in this state, an interruption request a' to an arithmetic part 2 is outputted in the period. Then, when the control line (c) is reset, i.e. when an instruction except a relay sequence head circuit instruction is read, the flip-flop 61 is reset, so that the signal a' is never outputted after this resetting even if a signal (c) is inputted before a signal (a) is inputted. When an interruption acceptance mode select input (d) goes up to a level H, on the other hand, an AND gate 65 is opened on condition that the signal (c) and the output of the flip-flop 61 are both at the level H, so that the request a' is outputted through a OR gate 67.

5. 发明专利

JPS62117001A Input and output processing method for programmable sequence controller 失效
标题翻译：可编程序控制器的输入和输出处理方法
公开(公告)号：JPS62117001A
公开(公告)日：1987-05-28
申请号：JP25583585
申请日：1985-11-16
申请人： Hitachi Ltd
发明人： FUJIWARA KATSUHIRO , OSHIGA TAKAYUKI , KASAHARA TOSHIRO
IPC分类号： G05B19/05
CPC分类号： G05B19/054
摘要： PURPOSE: To secure the application of a programmable sequence controller to any type of controlled system by reducing satisfactorily the scan time of the sequence controller with use of an image memory and at the same time coping with a desired controlled system in a satisfactorily short answer time less than a single scan time.
CONSTITUTION: When the input/output control instructions (I/O set and reset instructions) are supplied through an arithmetic part 3, the control lines (set and reset lines) delivered from an instruction decoding part 31 are changed. The set and reset lines are connected to the set and reset inputs of a flip-flop 43 respectively at an input/output control part 4. Then the output of the flip-flop 43 is changed every time the IOC set and reset instructions emerge and then supplied to a data selector 42. Thus the selector 43 selects the external input/ output data given directly from an input part 6 and an output part 7 or the data given from an input/output image memory 41 and sends it to the part 3.
COPYRIGHT: (C)1987,JPO&Japio
摘要翻译：目的：通过使用图像存储器令人满意地减少序列控制器的扫描时间，同时在令人满意的短的应答时间内处理所需的受控系统，从而确保将可编程序控制器应用于任何类型的受控系统少于单次扫描时间。构成：通过运算部3供给输入输出控制指令（I / O设定和复位指令）时，从指令译码部31发送的控制线（置位和复位线）发生变化。设置和复位线分别在触发器43的输入/输出控制部分4处连接到触发器43的设置和复位输入。然后，每当IOC置位和复位指令出现时，触发器43的输出被改变，并且然后提供给数据选择器42.因此，选择器43选择直接从输入部分6和输出部分7给出的外部输入/输出数据或从输入/输出图像存储器41给出的数据，并将其发送到部分3 。

6. 发明专利

JPS62109767A PACKER 失效
公开(公告)号：JPS62109767A
公开(公告)日：1987-05-20
申请号：JP24887685
申请日：1985-11-08
申请人： HITACHI LTD , HITACHI KEIYO ENG
发明人： AOKI TAKASHI , KOZUKA MICHIAKI , OSHIGA TAKAYUKI , FUJIWARA KATSUHIRO , KASAHARA TOSHIRO
IPC分类号： B65D61/00

7. 发明专利

JPS623303A SEQUENCE PROGRAM PRODUCING DEVICE 失效
公开(公告)号：JPS623303A
公开(公告)日：1987-01-09
申请号：JP14195885
申请日：1985-06-28
申请人： HITACHI LTD
发明人： ITO ATSUSHI , FUJIWARA KATSUHIRO
IPC分类号： G05B23/02 , G05B19/02 , G05B19/05 , G06F17/50
摘要： PURPOSE:To produce programs with use of a monitor having low resolution by displaying the symbols and contacts of the circuit component elements showing the mutual connection constitution and the codes of the relays, etc. at the position separate from each other and at the same time displaying the un-input symbols after discriminating them from each other. CONSTITUTION:A programming device contains a liquid crystal display device 14 and an input means. The device 14 includes a symbol display part 50 for display of symbols supplied from the input means and a code display part 51. A liquid crystal structure 52 showing a contact and its nearby connection constitution within the part 50 shows the make, break contacts, etc. and also that the code is not supplied yet to a contact symbol according to the light emitting state of each segment. A liquid crystal structure 65 showing a relay in the part 50 displays the type of a relay in response to the types of characters within the brackets. The part 51 consists of many dot segments and can display the Roman characters and numeric characters as well as the codes of contact, relays, etc.

8. 发明专利

JPS61264405A SEQUENCE CONTROLLER 失效
公开(公告)号：JPS61264405A
公开(公告)日：1986-11-22
申请号：JP10580785
申请日：1985-05-20
申请人： HITACHI LTD
发明人： ITO ATSUSHI , FUJIWARA KATSUHIRO
IPC分类号： G05B19/05 , G05B19/02
摘要： PURPOSE:To attain a high-speed response with a sequence controller by adding an arithmetic part and a program area for control of said arithmetic part to a controller part of an extension unit. CONSTITUTION:A basic unit 8 contains a storage part 8a, an arithmetic part 8b, an input part 8c and an output part 8d. A controller part 1 of an extension unit 3 transmits the data given from the unit 8 to an external I/O module 10. Then a single chip microcomputer 6 consisting of a RAM 2, a processor 4 and a ROM 5 is added to the part 1. Thus a controller 7 writes the data given from the unit 8 to the RAM 2 to complete the transfer of the external output data. The external input data is used to read the data out of the RAM 2 and transfer it to the unit 8. Thus an operation is carried out within the unit 3 in parallel with transmission of the external input signal to the unit 8. The result of this operation is delivered to outside.

9. 发明专利

JPS61136101A Input and output device 失效
标题翻译：输入和输出设备
公开(公告)号：JPS61136101A
公开(公告)日：1986-06-24
申请号：JP25750184
申请日：1984-12-07
申请人： Hitachi Ltd
发明人： OSAKO KAZUYOSHI , FUJIWARA KATSUHIRO , UMEDA KAZUNORI
IPC分类号： G05B15/02 , G05B15/00
摘要： PURPOSE: To attain the correct communication just with a single selection of an input/output card even with the data covering plural words, by setting an address for the own processing in addition to an address for selection of the input/output card itself and performing the next data communication, etc. with the input/output card through a CPU after said own processing is through.
CONSTITUTION: A 1-bit address line 7 is is provided newly together with an answer signal 8 used for transmission of an answer signal to a CPU 1 from each input/output card 3. The internal address of the card 3 is put on a data line 4 in addition to the original data. These are the main features of this input/output device. Furthermore the card 3 itself has a constitution different from the original one and contains an inverter 10, AND gates 11 and 12, registers 13 and 14, a card main body part 15, a timing generating circuit 16 and a flip-flop 17. The transmission of data is requested after the internal processing is over within the card 3. This eliminates such malfunctions as failures of data transmission, etching, etc.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：即使使用单个选择的输入/输出卡，即使覆盖多个字的数据，通过为输入/输出卡本身选择的地址除外设置自己的处理地址，并执行在通过自己的处理之后，通过CPU的输入/输出卡的下一次数据通信等。构成：与来自每个输入/输出卡3的CPU1的应答信号一起用于应答信号8，新提供1位地址线7.将卡3的内部地址置于数据第4行除原始数据外。这些是这个输入/输出设备的主要特征。此外，卡3本身具有与原来不同的结构，并且包含逆变器10，与门11和12，寄存器13和14，卡主体部分15，定时产生电路16和触发器17。内部处理结束后，请求数据传输。这样可以消除数据传输，蚀刻等故障。

10. 发明专利

JPS5949644A Arithmetic processing circuit of sequence controller 失效
标题翻译：序列控制器的算术处理电路
公开(公告)号：JPS5949644A
公开(公告)日：1984-03-22
申请号：JP15948382
申请日：1982-09-16
申请人： Hitachi Ltd
发明人： FUJIWARA KATSUHIRO , OKAMURA KOUSUKE
IPC分类号： G06F7/00 , G05B15/02 , G05B19/05 , G06F9/302 , G06F9/32
CPC分类号： G06F9/3001
摘要： PURPOSE:To inhibit the processing in an unnecessary stage, by altering or converting the output of a stage counter according to the kind of an instruction and the contents of an arithmetic result register. CONSTITUTION:An arithmetic control part 2 reads an instruction code (k) in an FF4 by the input of a latch signal l. Then, values of instruction codes (c) and (d) are identified and a clear command is supplied to the stage counter 1 at the time of an instruction NOP (allowing no process in the step except the advance of only the address counter of a program memory). Then, an advance to the next instruction fetch is made. The output (a) of the counter 1 is raised to ''1'' at the time of an instruction accompanying the input or output of external control data. The control part 2 sends out an operation mode code which means the input or output as an output (a) according to the condition between outputs (a) and (c) to perform specific operation. At the time of a conditional jump instruction, processing is performed according to the values of the output (a) of the counter 1 and the output (c) of the FF4.
摘要翻译：目的：通过根据指令的种类和算术结果寄存器的内容改变或转换级计数器的输出来禁止不必要的处理。构成：运算控制部分2通过锁存信号l的输入读取FF4中的指令代码（k）。然后，指示代码（c）和（d）的值被识别，并且在指令NOP时向阶段计数器1提供清除命令（除了只有地址计数器的前进之外，不允许在步骤中的处理程序存储器）。然后，进行下一个指令提取。在伴随外部控制数据的输入或输出的指令时，计数器1的输出（a）升高到“1”。控制部分2根据输出（a）和（c）之间的条件，发出一个意味着输入或输出作为输出（a）的操作模式代码，以执行特定操作。在条件跳转指令时，根据计数器1的输出（a）和FF4的输出（c）的值进行处理。

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