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1. 发明专利

JPS5950643A Receiving circuit of serial bit data 失效
标题翻译：接收串行数据的电路
公开(公告)号：JPS5950643A
公开(公告)日：1984-03-23
申请号：JP15948882
申请日：1982-09-16
申请人： Hitachi Ltd
发明人： OKAMURA KOUSUKE
IPC分类号： H04L25/40
CPC分类号： H04L25/40
摘要： PURPOSE:To improve the reliability of a system and its function, by storing an input serial bit data in the shift pulse period, using a gate circuit output outputting the content as a clear signal, and generating a sampling pulse so as to prevent mis-receiving even when impulsive noise exists. CONSTITUTION:A positive noise pulse is fetched in shift registers 1-3, and since an FF7 is set, an output of an AND gate 5 is inhibited at a signal line 14, and no clear signal 12 of a sampling counter 6 is outputted. The FF7 is reset via a signal line 15 at the leading when a value 1 of serial bit data is received. The FF7 stores the correct trailing of the serial bit data until the detection of trailing of the next estimated bit data and inhibits an output of the clear signal of the counter 6, then the counter 6 is not cleared erroneously by the trailing edge of noise pulse.
摘要翻译：目的：为了提高系统的可靠性及其功能，通过将输入串行位数据存储在移位脉冲周期内，使用输出内容作为清除信号的门电路输出，并产生采样脉冲，甚至当脉冲噪声存在时也能接收。构成：在移位寄存器1-3中取出正的噪声脉冲，并且由于设置了FF7，所以在信号线14处禁止AND门5的输出，并且不输出采样计数器6的清零信号12。当接收到串行位数据的值1时，FF7通过信号线15在引导时复位。 FF7存储串行位数据的正确尾数，直到检测下一个估计位数据的尾随，并禁止计数器6的清零信号的输出，则计数器6不会被噪声脉冲的后沿错误地清除。

2. 发明专利

JPS5949644A Arithmetic processing circuit of sequence controller 失效
标题翻译：序列控制器的算术处理电路
公开(公告)号：JPS5949644A
公开(公告)日：1984-03-22
申请号：JP15948382
申请日：1982-09-16
申请人： Hitachi Ltd
发明人： FUJIWARA KATSUHIRO , OKAMURA KOUSUKE
IPC分类号： G06F7/00 , G05B15/02 , G05B19/05 , G06F9/302 , G06F9/32
CPC分类号： G06F9/3001
摘要： PURPOSE:To inhibit the processing in an unnecessary stage, by altering or converting the output of a stage counter according to the kind of an instruction and the contents of an arithmetic result register. CONSTITUTION:An arithmetic control part 2 reads an instruction code (k) in an FF4 by the input of a latch signal l. Then, values of instruction codes (c) and (d) are identified and a clear command is supplied to the stage counter 1 at the time of an instruction NOP (allowing no process in the step except the advance of only the address counter of a program memory). Then, an advance to the next instruction fetch is made. The output (a) of the counter 1 is raised to ''1'' at the time of an instruction accompanying the input or output of external control data. The control part 2 sends out an operation mode code which means the input or output as an output (a) according to the condition between outputs (a) and (c) to perform specific operation. At the time of a conditional jump instruction, processing is performed according to the values of the output (a) of the counter 1 and the output (c) of the FF4.
摘要翻译：目的：通过根据指令的种类和算术结果寄存器的内容改变或转换级计数器的输出来禁止不必要的处理。构成：运算控制部分2通过锁存信号l的输入读取FF4中的指令代码（k）。然后，指示代码（c）和（d）的值被识别，并且在指令NOP时向阶段计数器1提供清除命令（除了只有地址计数器的前进之外，不允许在步骤中的处理程序存储器）。然后，进行下一个指令提取。在伴随外部控制数据的输入或输出的指令时，计数器1的输出（a）升高到“1”。控制部分2根据输出（a）和（c）之间的条件，发出一个意味着输入或输出作为输出（a）的操作模式代码，以执行特定操作。在条件跳转指令时，根据计数器1的输出（a）和FF4的输出（c）的值进行处理。

3. 发明专利

JPS5339029A COMMUNICATION CONTROL DEVICE 失效
公开(公告)号：JPS5339029A
公开(公告)日：1978-04-10
申请号：JP11310976
申请日：1976-09-22
申请人： HITACHI LTD
发明人： OKAMURA KOUSUKE
IPC分类号： H04L29/14 , G06F3/00 , G06F13/00
摘要： PURPOSE:To leave the minimum necessary information consecutively in a specified memory area in the form of a career until various faults of the circuit are displayed, and to realize a means through which the various faults can be detected easily and quickly based on the minimum necessary information.

4. 发明专利

JPS57172596A PROTECTION SYSTEM FOR MEMORY CONTENTS 失效
公开(公告)号：JPS57172596A
公开(公告)日：1982-10-23
申请号：JP5717581
申请日：1981-04-17
申请人： HITACHI LTD
发明人： OKAMURA KOUSUKE
IPC分类号： G06F12/14 , G05B19/05 , G06F11/00
摘要： PURPOSE:To prevent the contents of a specific memory from being modified in case of the runaway of a central processing part due to an intermittent fault, by controlling writing to a memory through the central processing part on the basis of an external control signal. CONSTITUTION:A flip-flop 9 is normally in a reset state, and set under the control of a peripheral equipment only for the modification or editing of a user's program, so that an address specifying part 4 attains writing address to a memory part 5 for the first time. While the flip-flop 9 is set, an arithmetic processing control part 1 controls the address specifying part 4 under the control of a system program regarding the modification or editing in response to a write request from the peripheral equipment through a peripheral-equipment control part 8. Consequently, while reading operation is performed upon occasion, memory access to desired addresses for writing is performed to modify or edit the contents of the memory part 5, namely, the user's program as desired.

5. 发明专利

JPS5567265A TEST SYSTEM OF AUTOMATIC CALLING CIRCUIT 失效
公开(公告)号：JPS5567265A
公开(公告)日：1980-05-21
申请号：JP13989778
申请日：1978-11-15
申请人： HITACHI LTD
发明人： OKAMURA KOUSUKE , SHIMODA SEIJI
IPC分类号： H04M11/06 , H04L29/10 , H04L29/14 , H04M3/24 , H04M11/00
摘要： PURPOSE:To make self-testing of an automatic calling circuit possible without addition of a testing circuit by using two sets of automatic calling circuits and a loop cable. CONSTITUTION:Two sets of automatic calling circuits 4 are provided in automatic calling buffer 2, and each circuit 4 is connected to network control unit 3 through interface cable 6 by circuit control part 1 and a control program. For the operation test of circuits 4, cable 6 of one circuit 4(A) is removed, and this circuit and the other circuit 4(B) are connected by loop cable 7. Next, when circuit 9 of control part 1 sends signals to register group 10 of circuit 4(A) through line 12, signals from register group 10 are sent to circuit 4(B) through level conversion circuit 11 and cable 7, and output signals are stored in data register 8 through line 13. Then, coincidence and incoincidence of transmission and receiving information are detected by the control program.

6. 发明专利

JPS5250663A CLASSIFICATION INSTRUCTION CONTROL SYSTEM 失效
公开(公告)号：JPS5250663A
公开(公告)日：1977-04-22
申请号：JP12636375
申请日：1975-10-22
申请人： HITACHI LTD
发明人： KIHARA KENJI , OOAMI MICHIMUTSU , OKAMURA KOUSUKE
IPC分类号： G06F9/32 , G06F9/06
摘要： PURPOSE:To reduce the diverged address store area corresponding to the number of classification to be used by making a program control using IDB instruction, and also to attain the economization optionally designating the beginning address of the store area.

7. 发明专利

JPS5719807A SEQUENCE CONTROLLER 失效
公开(公告)号：JPS5719807A
公开(公告)日：1982-02-02
申请号：JP9276480
申请日：1980-07-09
申请人： HITACHI LTD
发明人： OKAMURA KOUSUKE
IPC分类号： G05B23/02 , G05B19/042
摘要： PURPOSE:To check whether a sequence controller (SQCT) operates normally or not when it is started, by providing an FF showing a diagnostic mode when an electric power source is put to work, and a memory for storing a program for checking an operation. CONSTITUTION:When an elctric power source is turned on, an FF8 showing a diagnostic mode for checking an operation of an SQCT is set through an electric power source on signal line 13, and its diagnostic mode is indicated to a program counter 3 and an input/output control part 4 through a signal line 12. A counter 3 accesses only a memory 10 for storing a basic instruction of the SQCT which is a part of a user program area, and a diagnostic result. The control part 4 inhibits input/output of input/output information through a signal line 14. After the electric power source has been turned on, an operation control part 1 executes a diagnostic program stored in a memory area 9 at first, checks whether a basic instruction executed by the control part 1 is executed normally or not, and whether read and write of the memory 10 can be executed normally or not, shifts the basic instruction of the memory 9 to the memory 10, and checks the operation.

8. 发明专利

JPS55159655A COMMUNICATION CONTROL PROCESSOR 失效
公开(公告)号：JPS55159655A
公开(公告)日：1980-12-11
申请号：JP6721579
申请日：1979-05-30
申请人： HITACHI LTD
发明人： OKADA YOUICHI , OKAMURA KOUSUKE
IPC分类号： H04L29/04 , G06F13/00 , H04L12/26 , H04L29/14
摘要： PURPOSE:To make easy maintenance and diagnosis, by previously storing the adaptor-mounted information in the register provided in the line control section and enabling to retrieve the adaptor information and its type by the diagnosis program. CONSTITUTION:The adaptor-mounted information is stored in advance in the line control register of the line control section 2 in the scan timing in synchronizing with the scanning of line, and it is made retrievable with the diagnosis program as required. Thus, the maintenance and diagnosis can easily be made by enabling to retrieve the adaptor information and type for the mounted information accurately in a short time.

9. 发明专利

JPS5250664A CLASSIFICATION INSTRUCTION CONTROL SYSTEM 失效
公开(公告)号：JPS5250664A
公开(公告)日：1977-04-22
申请号：JP12636475
申请日：1975-10-22
申请人： HITACHI LTD
发明人： OKAMURA KOUSUKE , KIHARA KENJI , OOAMI MICHIMUTSU
IPC分类号： G06F9/32
摘要： PURPOSE:The program control by the MLTJ instruction is made in order to discriminate the classification cause at a time and to diverge same to the handling program position, and the diverged address which has something in common with the classfication is used commonly so as to reduce the memory area and attain the economization.

10. 发明专利

JPS6111805A Sequence control device 失效
标题翻译：序列控制设备
公开(公告)号：JPS6111805A
公开(公告)日：1986-01-20
申请号：JP13100884
申请日：1984-06-27
申请人： Hitachi Ltd
发明人： KASAHARA TOSHIROU , OKAMURA KOUSUKE , OSHIGA TAKAYUKI , ITOU ATSUSHI
IPC分类号： G05B19/05 , G05B19/07
CPC分类号： G05B19/07
摘要： PURPOSE:To synchronize the transmission/reception of data easily by forming a flag storing part to be accessed from respective operation parts and determining the execution of processing of the succeeding instruction or after on the basis of the status whether the flag storing part is set or not. CONSTITUTION:In a sequence control device, operation parts 3, 4 execute the operation of data inputted from an external apparatus 8 through an input part 6 in accordance with a program stored in storage parts 1, 2 and transfers the operated result to the external apparatus 8 through an output part 7. In this case, the flag storing part 9 to be directly accessed from respective operation parts 3, 4 is formed to store an instruction for jumping its operation to a specified address if the flag is set up or executing the succeeding instruction, and if not set up, setting up the flag and executing the succeeding instruction without jump and also storing an instruction for resetting the flag. Consequently, the synchronization of the transmission/reception of data between plural programs can be guaranteed.
摘要翻译：目的：通过形成要从各个操作部分访问的标志存储部分并确定执行后续指令或者基于标志存储部分被设置的状态之后，容易地同步数据的发送/接收不。构成：在顺序控制装置中，操作部3,4根据存储在存储部1,2中的程序，通过输入部6执行从外部装置8输入的数据的动作，将操作结果传送到外部装置在这种情况下，形成从相应的操作部分3,4直接访问的标志存储部分9，如果标志被建立或执行，则形成用于将其操作跳转到指定地址的指令后续指令，如果没有设置，则设置标志并执行后续指令而不跳转，并且还存储用于复位标志的指令。因此，可以保证多个程序之间的数据的发送/接收的同步。

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