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1. 发明专利

JP2010038853A Method and device for inspecting substrate surface 有权
标题翻译：用于检查基板表面的方法和装置
公开(公告)号：JP2010038853A
公开(公告)日：2010-02-18
申请号：JP2008205097
申请日：2008-08-08
申请人： Ebara Corp , Toshiba Corp , 株式会社東芝 , 株式会社荏原製作所
发明人： NAITO YOSHIHIKO , KIMURA NORIO , TERAO KENJI , HATAKEYAMA MASAKI , ITO MASAMITSU
IPC分类号： G01N23/225 , G03F1/84 , G03F1/86
CPC分类号： G01N23/203 , G01N2223/652
摘要： PROBLEM TO BE SOLVED: To provide a method and device for inspecting a substrate surface for easily and accurately detecting a defect existing on the substrate surface using cell inspection. SOLUTION: This method for inspecting the substrate surface for detecting the defect 32 on the substrate 10 containing a plurality of materials on the surface includes an electron beam irradiating process of irradiating the surface of the substrate with the electron beam to which a landing energy is set so that the contrast of at least two kinds of materials of the plurality of materials is within a predetermined range, a process of detecting an electron generated from the substrate and acquiring a surface image of the substrate while a pattern made of the two kinds of materials is eliminated or thinned, and a process of detecting, as the defect 32, an image of a target having a contrast distinguishable from the background image in the obtained surface image. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于检查基板表面的方法和装置，以便容易且准确地检测使用电池检查存在于基板表面上的缺陷。解决方案：用于检测在表面上含有多种材料的基板10上的缺陷32的检测用基板表面的方法包括电子束照射工序，用电子束照射基板的表面，能量被设定为使得多种材料中的至少两种材料的对比度在预定范围内，检测从衬底产生的电子并获取衬底的表面图像的过程，同时由两个材料形成的图案将各种材料消除或变薄，以及作为缺陷32检测在所获得的表面图像中具有与背景图像可辨别的对比度的对象的图像的处理。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010002772A Pattern verification-inspection method, method for acquiring distribution of optical image intensity, and program for acquiring distribution of optical image intensity 审中-公开
标题翻译：图形验证检验方法，获取光学图像强度分布的方法，以及获取光学图像强度分布的程序
公开(公告)号：JP2010002772A
公开(公告)日：2010-01-07
申请号：JP2008162508
申请日：2008-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU , TANAKA SATOSHI
IPC分类号： G03F1/36 , G03F1/68 , H01L21/027
CPC分类号： G03F1/86
摘要： PROBLEM TO BE SOLVED: To obtain a pattern verification-inspection method by which a pattern dimension of a mask pattern is inspected with high accuracy.
SOLUTION: The pattern verification-inspection method for inspecting a pattern dimension of a mask pattern formed in a photomask includes: an illumination condition deriving step of deriving illumination conditions at the position of an inspection object based on the position of the inspection object that is the position of a mask pattern as an inspection object within the photomask plane and based on the distribution of illumination conditions within the photomask plane of the exposure light irradiating the photomask by an exposure apparatus; a simulation step of carrying out lithographic simulation of the mask pattern at each position of the inspection object based on the illumination conditions at the position of the inspection object and the pattern contour of the mask pattern; and a verification-inspection step of inspecting the pattern dimension based on the result of the lithography simulation.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：获得以高精度检查掩模图案的图案尺寸的图案验证检查方法。解决方案：用于检查形成在光掩模中的掩模图案的图案尺寸的图案验证检查方法包括：基于检查对象的位置导出检查对象位置处的照明条件的照明条件导出步骤即作为光掩模平面内的检查对象的掩模图案的位置，并且基于通过曝光装置照射光掩模的曝光光的光掩模面内的照明条件的分布; 基于检查对象的位置的照明条件和掩模图案的图案轮廓，对检查对象的各位置处的掩模图案进行光刻模拟的模拟步骤; 以及基于光刻仿真的结果检查图案尺寸的验证检查步骤。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009141263A Exposure method, photo mask and reticle stage 审中-公开
标题翻译：曝光方法，照片掩蔽和反应阶段
公开(公告)号：JP2009141263A
公开(公告)日：2009-06-25
申请号：JP2007318574
申请日：2007-12-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KONO TAKUYA , NAKASUGI TETSUO , TOKI TATSUHIKO , ITO MASAMITSU
IPC分类号： H01L21/027 , G03F1/68 , G03F7/20
CPC分类号： G03F7/70433 , G03F7/70066 , G03F7/70425
摘要： PROBLEM TO BE SOLVED: To provide an exposure method by which a pattern dimension in a wafer surface is stabilized and a wafer is exposed at a high throughput. SOLUTION: A product region Ax for exposing a center portion 91 of a wafer 8 and a peripheral exposure region Bx for exposing a peripheral portion 92 of the wafer 8 are provided. The method of this invention includes an opening step wherein, when the peripheral portion 92 is exposed by using a photo mask 6 which is so formed that the peripheral exposure region Bx becomes a region containing a plurality of kinds of pattern density, one or more predetermined regions on the photo mask are so opened by blinds 4P-4S that the one or more predetermined regions selected out from the inside of the peripheral exposure region Bx have a pattern density corresponding to a shot position of the peripheral portion 92, and an exposure step wherein the wafer 8 is irradiated with an exposure light from the opened one or more predetermined regions to expose the peripheral portion 92. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种曝光方法，通过该方法，晶片表面的图案尺寸稳定，晶片以高生产量曝光。解决方案：提供用于暴露晶片8的中心部分91的产品区域Ax和用于暴露晶片8的周边部分92的周边曝光区域Bx。本发明的方法包括一个打开步骤，其中当通过使用形成为周边曝光区域Bx成为包含多种图案密度的区域的光掩模6来曝光外围部分92时，一个或多个预定的通过百叶窗4P-4S将光掩模上的区域打开，从周边曝光区域Bx的内部选出的一个或多个预定区域具有对应于周边部分92的拍摄位置的图案密度，曝光步骤其中晶片8被来自打开的一个或多个预定区域的曝光光照射以露出周边部分92.版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008233687A Pattern information generating method 有权
标题翻译：模式信息生成方法
公开(公告)号：JP2008233687A
公开(公告)日：2008-10-02
申请号：JP2007075482
申请日：2007-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ASANO MITSUYO , TANAKA SATOSHI , YAMAGUCHI SHINJI , ITO MASAMITSU , IKENAGA OSAMU , INOUE SOICHI
IPC分类号： G03F1/84 , G03F1/86 , G06T1/00 , G06T3/00
CPC分类号： G06T7/001 , G03F1/86 , G06T2207/10056 , G06T2207/30148
摘要： PROBLEM TO BE SOLVED: To provide a pattern information generating method in which suitable pattern information can be generated. SOLUTION: The pattern information generating method includes a stage S11 of acquiring an image of a mask pattern; a stage S13 of matching the image of the mask pattern with a reference pattern; a stage S14 of setting reference points at a contour of the reference pattern at set intervals corresponding to distances from a vertex of the reference pattern; and a stage S15 of outputting contour points of the image of the mask pattern to positions predefined by the reference points. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以生成合适的图案信息的图案信息生成方法。解决方案：图案信息生成方法包括获取掩模图案的图像的阶段S11; 将掩模图案的图像与参考图案进行匹配的阶段S13; 在参考图案的轮廓处以与参考图案的顶点的距离对应的设定间隔设置参考点的阶段S14; 以及将掩模图案的图像的轮廓点输出到由参考点预定义的位置的台S15。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007025366A Method for manufacturing mask, method for measuring flatness of mask, pellicle mounting device, and method for manufacturing semiconductor device 审中-公开
标题翻译：用于制造掩模的方法，用于测量掩模的平滑度的方法，油墨安装装置以及制造半导体器件的方法
公开(公告)号：JP2007025366A
公开(公告)日：2007-02-01
申请号：JP2005208780
申请日：2005-07-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/62 , G03F7/20 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a mask for obtaining flatness of a mask as predicted by an actual exposure apparatus, and to provide a method for measuring flatness of a mask, a pellicle mounting device and a method for manufacturing a semiconductor device. SOLUTION: The method for manufacturing a mask includes a step of mounting a pellicle on an exposure mask, wherein in the step (S110) of mounting the pellicle, a first humidity in the environment where the pellicle is exposed is controlled to be lower than a second humidity in the environment where an exposure mask mounting the pellicle is exposed in a predetermined exposure apparatus. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于制造用于获得由实际曝光装置预测的掩模的平坦度的掩模的方法，并且提供一种用于测量掩模的平整度的方法，防护薄膜组件安装装置和用于制造半导体器件。解决方案：掩模的制造方法包括将防护薄膜组件安装在曝光掩模上的步骤，其中在安装防护薄膜组件的步骤（S110）中，将防护薄膜组件暴露的环境中的第一湿度控制为在安装防护薄膜的曝光掩模在预定曝光装置中露出的环境中低于第二湿度。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006210840A Pattern forming method, manufacturing method of photomask, manufacturing method of semiconductor device and program 有权
标题翻译：图案形成方法，光电子制造方法，半导体器件和程序的制造方法
公开(公告)号：JP2006210840A
公开(公告)日：2006-08-10
申请号：JP2005024142
申请日：2005-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKURAI HIDEAKI , SHIBATA TORU , SAITO MASATO , ITO MASAMITSU
IPC分类号： H01L21/027 , G03F1/76 , G03F1/78 , G03F7/20
CPC分类号： G03F7/70625 , G03F7/70558 , Y10S430/143
摘要： PROBLEM TO BE SOLVED: To realize a pattern forming method capable of suppressing development inhibition caused by a development by-product produced at the time of development to decrease errors in dimensions. SOLUTION: The pattern forming method includes a process that forms a resist film on the principal plane of a substrate, a process that exposes the resist film, a process that develops the resist film by letting a developer to flow on the resist film, and a process that forms a pattern on the substrate by letting the substrate to be etched with the resist film as a mask. The process that exposes the resist film includes a process S1 that divides the principal plane of the substrate into M (≥2) regions and a process which is processes S2 to S4 that each determine a corrected exposure value in N regions, and determines a corrected exposure value of the i-th (1≤i≤M) region so as to allow actual pattern dimensions in the i-th region to be designed pattern dimensions, based on the pattern opening rate relative to a pattern in a region upstream the i-th region in the upstream direction in the flow of the developer. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了实现能够抑制由显影时产生的显影副产物引起的显影抑制以减小尺寸误差的图案形成方法。解决方案：图案形成方法包括在基板的主平面上形成抗蚀剂膜的工艺，曝光抗蚀剂膜的工艺，通过使显影剂在抗蚀剂膜上流动来显影抗蚀剂膜的工艺以及通过使基板被抗蚀剂膜作为掩模进行蚀刻而在基板上形成图案的工艺。曝光抗蚀剂膜的处理包括：将基板的主面分割为M（≥2）区域的处理S1，以及处理S2〜S4的处理，各处理N个区域中的修正曝光值，并确定修正后的处理基于相对于i上游区域中的图案的图案开度，第i（1≤i≤M）区域的曝光值，以便允许第i区域中的实际图案尺寸被设计为图案尺寸在显影剂流动的上游方向上的第三区域。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006039223A Method for manufacturing exposure mask, exposure apparatus, method for manufacturing semiconductor device, and mask blank product 有权
标题翻译：用于制造曝光掩模的方法，曝光装置，制造半导体器件的方法和掩模产品
公开(公告)号：JP2006039223A
公开(公告)日：2006-02-09
申请号：JP2004219178
申请日：2004-07-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/50 , G03F1/68 , G03F7/20 , H01L21/027
CPC分类号： G03F1/70
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a photomask for preventing displacement of a mask pattern. SOLUTION: The method for manufacturing a photomask includes: a step of preparing flatness variation data 2b relating to a mask blank substrate; a step of generating position correction data 5 of a pattern to be drawn on the mask blank substrate based on the flatness variation data 2b so as to place the mask pattern at a predetermined position on the photomask while the photomask is chucked by a chucking means of an exposure apparatus; and a step of drawing a pattern on the mask blank substrate, wherein drawing data 6 and the position correction data 5 corresponding to the pattern are inputted in a drawing apparatus to draw a pattern while correcting the drawing position of the pattern. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造防止掩模图案位移的光掩模的方法。解决方案：制造光掩模的方法包括：制备与掩模坯料基板相关的平坦度变化数据2b的步骤; 基于平坦度变化数据2b产生要在掩模坯料基板上绘制的图案的位置校正数据5的步骤，以将掩模图案放置在光掩模上的预定位置，同时光掩模被夹持装置夹持曝光装置; 以及在掩模空白基板上绘制图案的步骤，其中绘制数据6和与图案对应的位置校正数据5被输入到绘图装置中以在校正图案的绘制位置的同时绘制图案。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005043830A Substrate for photomask blank, photomask blank, and photomask 有权
标题翻译：照片BITEK，PHOTOMASK BLANK和PHOTOMASK
公开(公告)号：JP2005043830A
公开(公告)日：2005-02-17
申请号：JP2003280437
申请日：2003-07-25
申请人： Nikon Corp , Shin Etsu Chem Co Ltd , Toshiba Corp , 信越化学工業株式会社 , 株式会社ニコン , 株式会社東芝
发明人： NAKATSU MASAYUKI , NUMANAMI TSUNEO , MOGI TADAYUKI , ITO MASAMITSU , HAGIWARA TSUNEYUKI , KONDO NAOHITO
IPC分类号： G03F1/26 , G03F1/60 , H01L21/027 , G03F1/14
摘要： PROBLEM TO BE SOLVED: To provide a substrate for a photomask blank resulting in a photomask with which a refined pattern can be drawn on a wafer substrate by exposure with high accuracy, and to provide a photomask blank and a photomask using the substrate.
SOLUTION: In a square annular region from 2 mm to 10 mm inside the side lines which form the peripheral edge of the upper face of the substrate where a mask pattern is to be formed, the least square plane of the square annular region is defined as the reference plane. When a circle centered on the center of the substrate is drawn on the reference plane to intersect with the reference plane, the substrate for a photomask blank shows ≤0.3 μm difference between the maximum height and the minimum height of the arc portion drawn over the reference plane from the reference plane. The substrate shows a favorable surface flat profile on exposing a wafer. By using the above substrate to manufacture a photomask blank and further by processing the blank into a photomask, the mask has little warpage of the substrate surface and shows high flatness when the photomask is fixed by a vacuum chuck or the like to the mask stage of a wafer aligner, and therefore, a fine exposure pattern can be drawn on the wafer with accurate positions and width.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于光掩模坯料的基板，其产生光掩模，通过高精度地曝光可以在晶片衬底上绘制精制图案，并且使用该基板提供光掩模坯料和光掩模。解决方案：在形成要形成掩模图案的基板的上表面的周缘的侧线内的2mm至10mm的方形环形区域中，方形环形区域的最小二乘平面被定义为参考平面。当以基板中心为中心的圆在参考平面上被绘制为与参考平面相交时，用于光掩模坯料的基板在参考点上绘制的弧形部分的最大高度和最小高度之间的差值为0.3μm以下平面从参考平面。衬底在暴露晶片时显示出有利的表面平坦轮廓。通过使用上述基板来制造光掩模坯料，并且通过将坯料加工成光掩模，掩模在基板表面的弯曲变小，当通过真空卡盘等将光掩模固定到掩模台晶片对准器，因此，精确的位置和宽度可以在晶片上绘制精细的曝光图案。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004045501A Photomask, method for manufacturing photomask, and method for manufacturing electronic component 有权
公开(公告)号：JP2004045501A
公开(公告)日：2004-02-12
申请号：JP2002199918
申请日：2002-07-09
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO SACHIYO , ITO MASAMITSU , HASUNUMA MASAHIKO
IPC分类号： G03C5/00 , G03F1/32 , G03F1/68 , G03F7/09 , G03F9/00 , H01L21/00 , H01L21/027 , G03F1/08
CPC分类号： G03F1/32
摘要： PROBLEM TO BE SOLVED: To provide a photomask having desired flatness. SOLUTION: The photomask 10 is constituted of a quartz substrate 1, a translucent film 2 selectively formed on the quartz substrate 1, and a light shielding film 3 selectively formed on the translucent film 2. When the Young's moduli (MPa) of the quartz substrate 1, the translucent film 2, and the light shielding film 3 are E 0 , E 1 , and E 2 respectively; the thicknesses (m) are d 0 , d 1 , and d 2 respectively; the internal stresses (MPa) of the translucent film 2 and the light shielding film 3 at room temperature are respectively s 1 and s 2 ; the coating ratio of the translucent film 2 in the area where the light shielding film 3 is not formed is h, and the coefficients k 1 to k 4 are respectively k 1 =1.3×10 -8 , k 2 =-9.5×10 -2 , k 3 =6.0×10 -7 , k 4 =-5.2×10 -2 , the following condition is satisfied: ¾1/E 0 d 0 äh(k 1 s 1 /E 1 d 1 +k 2 )+(k 3 s 1 /E 1 d 1 +k 4 )}¾≤1.4×10 -4 (m -1 ). COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2003050458A Method for manufacturing exposure mask, method for generating mask base plate information, method for manufacturing semiconductor device, mask base plate, exposure mask and server 有权
标题翻译：用于制造曝光掩模的方法，用于生成掩模基板信息的方法，制造半导体器件的方法，掩模基板，曝光掩模和服务器
公开(公告)号：JP2003050458A
公开(公告)日：2003-02-21
申请号：JP2002054919
申请日：2002-02-28
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MASAMITSU
IPC分类号： G03F1/60 , G03F7/20 , H01L21/00 , H01L21/027 , G03F1/14
摘要： PROBLEM TO BE SOLVED: To realize a method for manufacturing an exposure mask which is effective to solve a problem on the lowering of the yield of a product caused by the deterioration of the flatness of a mask base plate by chucking the mask base plate on the mask stage of a wafer aligner. SOLUTION: The surface shape of the principal surface of each of a plurality of mask base plates and the flatness of the principal surface thereof before and after chucking the mask base plate on the mask stage of the aligner are acquired (step S3), the mask base plate having the surface shape having good flatness both before and after it is chucked on the mask stage is prepared (step S5), and a desired pattern is formed on the mask base plate, whereby the exposure mask is formed (step S6).
摘要翻译：要解决的问题：实现一种制造曝光掩模的方法，其有效地解决了通过将掩模基板夹持在掩模基板上而使掩模基板的平坦度劣化所引起的产品的产量下降的问题晶片对准器的掩模阶段。解决方案：获取多个掩模基板中的每一个的主表面的表面形状以及将掩模基板夹持在对准器的掩模台上之前和之后的主表面的平面度（步骤S3），掩模准备在掩模台上夹持之前和之后具有良好平坦度的基板（步骤S5），并且在掩模基板上形成期望的图案，从而形成曝光掩模（步骤S6）。

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