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1. 发明专利

JP2012164817A Multilayer wiring board 审中-公开
标题翻译：多层接线板
公开(公告)号：JP2012164817A
公开(公告)日：2012-08-30
申请号：JP2011024170
申请日：2011-02-07
申请人： Murata Mfg Co Ltd , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 株式会社村田製作所
发明人： YAMANAGA ISAO , ICHIMURA TAKASHI , AZUMA TAKAHIRO , AKIMOTO TETSUYA , KARIYAZAKI SHUICHI , SHIRAI WATARU , TSUKUDA TATSUAKI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can reduce power supply impedance at an antiresonant frequency while keeping the power supply impedance at a resonant frequency low.SOLUTION: Between a power source and a ground of an IC 50 mounted on a multilayer wiring board 1, one or more (two in Fig. 1) high ESR capacitors 70 each having an ESL of 1 nH or less and an ESR of no fewer than 1.5 Ω nor more than 20 Ω, and one or more (two in Fig. 1) low ESR capacitors 60 each having an ESL of 1 nH or less and an ESR of 100 mΩ or less are connected in parallel. The multilayer wiring board 1 can reduce impedance at an antiresonant frequency less than half (equivalent of -6 dB noise reduction) in comparison with the case provided with only low ESR capacitors 60, while keeping power supply impedance at a resonant frequency low.
摘要翻译：要解决的问题：提供一种能够在将电源阻抗保持在谐振频率低的同时降低反谐振频率下的电源阻抗的多层布线基板。解决方案：在安装在多层布线板1上的IC 50的电源和地之间，一个或多个（图1中的两个）高ESR电容器70各自具有1nH以下的ESL和ESR 不小于1.5Ω且不大于20Ω，并且并联连接一个或多个（图1中的两个）具有1nH以下的ESL和100mΩ以下的ESR的低ESR电容器60。与仅提供低ESR电容器60的情况相比，多层布线板1可以将谐振频率低的电源阻抗保持在小于半（相当于-6dB噪声降低）的反谐振频率处的阻抗。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011204733A Wiring board and method of manufacturing the same 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2011204733A
公开(公告)日：2011-10-13
申请号：JP2010067894
申请日：2010-03-24
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KARIYAZAKI SHUICHI
IPC分类号： H05K3/42
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/49838 , H01L2924/0002 , Y10T29/49155 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board capable of more rapid signal transmission, and a method of manufacturing the wiring board.SOLUTION: The wiring board includes a sidewall conductive layer 3 and a land 4. The sidewall conductive layer 3 is formed on a sidewall of a through hole 2 opened on a substrate 1. The land 4 is a conductive layer connected with the sidewall conductive layer 3 in which only a land portion 11 as a minimum necessary portion used for wiring is formed on a surface of the substrate 1. An unnecessary portion 12 of the land 4 other than the land portion 11 is eliminated. Thus, by eliminating the unnecessary portion of the land 4 while leaving the minimum necessary portion for use in wiring, an unnecessary wiring capacitance of wiring capacitance of the land 4 can be reduced. Thus, a "time constant" expressed by a multiplication of wiring resistance R and wiring capacitance C can be made small enough and rising or falling speed of a signal can be accelerated, thereby allowing more rapid signal transmission.
摘要翻译：要解决的问题：提供能够更快速地进行信号传输的布线板以及布线板的制造方法。解决方案：布线板包括侧壁导电层3和焊盘4.侧壁导电层3形成在在基板1上开口的通孔2的侧壁。焊盘4是与侧壁导电层3连接的导电层，其中仅在基板的表面上形成用作布线的最小必需部分的焊盘部分11 消除了陆地部分11以外的陆部4的不必要部分12。因此，通过在留下用于布线的最小必要部分的同时消除焊盘4的不需要的部分，可以减少焊盘4的布线电容的不必要的布线电容。因此，可以使由布线电阻R和布线电容C的乘法表示的“时间常数”足够小，并且可以加速信号的上升或下降速度，从而允许更快速的信号传输。

3. 发明专利

JP2014116371A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014116371A
公开(公告)日：2014-06-26
申请号：JP2012267653
申请日：2012-12-06
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： OKADA MAKOTO , KARIYAZAKI SHUICHI , SHIRAI WATARU , SUZUHARA MASAFUMI , SERA NAOKO
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L25/0655 , H01L23/02 , H01L23/04 , H01L23/055 , H01L23/28 , H01L23/498 , H01L23/49816 , H01L23/562 , H01L24/33 , H01L2224/16225 , H01L2224/32225 , H01L2224/3224 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2924/1015 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/16251 , H01L2924/167 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve such problems that a board having a wider area is required for achieving a semiconductor device including a plurality of semiconductor chips mounted on the same board, a semiconductor device tends to cause warpage and distortion when an area of a board is increased while suppressing an increase in thickness of the board, and mounting a semiconductor device on a wiring board becomes difficult and impossible when warpage and distortion are caused in the semiconductor device.SOLUTION: Warpage in a semiconductor device can be suppressed by mounting two semiconductor chips on the same diagonal line of a board and mounting one of the semiconductor chips on the intersection point of the two diagonal lines of the board.
摘要翻译：要解决的问题为了解决这样的问题：为了实现包括安装在同一板上的多个半导体芯片的半导体器件，需要具有较宽面积的电路板，当板的面积变化时，半导体器件趋于产生翘曲和变形在抑制板的厚度增加的同时增加，并且在半导体器件中引起翘曲和变形时，难以并且不可能将半导体器件安装在布线板上。解决方案：可以通过安装两个半导体来抑制半导体器件中的翘曲芯片在板的相同对角线上，并且在板的两条对角线的交点上安装半导体芯片之一。

4. 发明专利

JP2014204057A 半導体装置及び配線基板有权
标题翻译：半导体器件和接线板
公开(公告)号：JP2014204057A
公开(公告)日：2014-10-27
申请号：JP2013081064
申请日：2013-04-09
申请人：ルネサスエレクトロニクス株式会社 , Renesas Electronics Corp
发明人： KARIYAZAKI SHUICHI , OIKAWA RYUICHI
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01L23/5222 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L2223/6616 , H01L2223/6655 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73153 , H01L2224/73204 , H01L2924/12042 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00012 , H01L2924/014 , H01L2924/00
摘要：【課題】コストを抑えつつ、良好な信号の伝送特性を実現する。【解決手段】半導体装置(100)は、半導体チップ(2)と配線基板(1)を有する。配線基板は、半導体チップに接続される規則的に配列された複数の第1及び第2信号電極(10_Rx、10_Tx)が形成された第1主面と第2主面の間に配線領域を有する。第1及び第2信号電極は、その配列中に分散して配置される。配線領域は、コア基板(21)と、その両面に形成された配線層(20、22)と、インピーダンス整合のための容量を形成する、複数の第1スルーホール(CR1)及び第1主面側の配線層を貫通する複数の第1ビア(CT1)を有する。第1スルーホールは、第1信号電極から第1配線長(LR1)だけ離れた位置で第1信号配線と接続され、第1ビアは、第2信号電極から第1配線長と実質的に等しい第2配線長(LT1)だけ離れた位置で第2信号配線と接続される。【選択図】図10
摘要翻译：要解决的问题：在保持成本低的同时实现良好的信号传输特性。解决方案：半导体器件（100）具有半导体芯片（2）和布线板（1）。布线板具有在第二主表面和第一主表面之间的布线区域，其上形成有与半导体芯片连接并规则排列的多个第一和第二信号电极（10_Rx，10_Tx）。第一和第二信号电极以分散的方式布置在排列中。布线区域具有：芯基板（21）; 形成在所述芯基板的两面上的布线层（20,22）以及穿过形成用于阻抗匹配的电容的第一主表面侧的布线层的多个第一通孔（CR1）和多个第一通孔（CT1）。第一通孔在与第一信号电极分离第一布线长度（LR1）的位置处连接到第一信号布线，并且第一通孔在与第二信号电极分离的位置处通过第二布线连接到第二信号布线长度（LT1）基本上等于第一布线长度。

5. 发明专利

JP2013074054A Electronic device, wiring board, and electronic device manufacturing method 审中-公开
标题翻译：电子设备，接线板和电子设备制造方法
公开(公告)号：JP2013074054A
公开(公告)日：2013-04-22
申请号：JP2011211399
申请日：2011-09-27
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KARIYAZAKI SHUICHI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H05K1/111 , H01L23/49838 , H01L23/50 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16105 , H01L2224/16106 , H01L2224/16225 , H01L2224/16237 , H01L2224/17051 , H01L2224/17104 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81385 , H01L2224/82385 , H01L2924/15311 , H05K1/0268 , H05K2201/09663 , H05K2201/10734 , H05K2201/10977 , Y02P70/611 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an electronic device whose electrodes are electrically connected together by using solder, as in the case of a semiconductor device composed by flip-chip connections, and in which the other parts having the electrodes of electronic components connected thereto can be switched over by a technique other than that which involves changing the circuits of electronic components such as chips or the circuits of wiring boards.SOLUTION: An electronic device (e.g., a semiconductor device 100) includes a wiring board 200 having a plurality of first electrodes 210 on the surface on one side of it and an electronic component (e.g., a chip 300) having a plurality of second electrodes 310 disposed facing each of the plurality of first electrodes 210 on the surface on one side of it. At least one or more of the first electrodes 210 are a specific electrode 220 which is divided into a plurality of divided sections 221 and 222, the divided sections 221 and 222 respectively being connected to different wirings 251 and 252. Either one or more of the divided sections 221 and 222 are connected to the corresponding second electrodes 310 via a solder 110.
摘要翻译：要解决的问题：提供一种电子器件，其电极通过使用焊料电连接在一起，如在由倒装芯片连接构成的半导体器件的情况下，其中具有电子部件的电极的其它部件可以通过除了包括改变诸如芯片的电子部件的电路或者布线板的电路的技术之外的技术来切换与其相连的技术。电子设备（例如，半导体器件100）包括布线板200，其布线板200在其一侧的表面上具有多个第一电极210以及具有多个第一电极的电子部件（例如，芯片300）第二电极310被布置为面对其一侧上的表面上的多个第一电极210中的每一个。第一电极210中的至少一个或多个是分隔成多个分割部分221和222的特定电极220，分隔部分221和222分别连接到不同的布线251和252。任一个或多个分割部分221和222通过焊料110连接到相应的第二电极310.版权所有：（C）2013，JPO＆INPIT

6. 发明专利

JP2012164816A Multilayer wiring board 审中-公开
标题翻译：多层接线板
公开(公告)号：JP2012164816A
公开(公告)日：2012-08-30
申请号：JP2011024169
申请日：2011-02-07
申请人： Murata Mfg Co Ltd , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 株式会社村田製作所
发明人： ICHIMURA TAKASHI , YAMANAGA ISAO , AZUMA TAKAHIRO , AKIMOTO TETSUYA , KARIYAZAKI SHUICHI , SHIRAI WATARU , TSUKUDA TATSUAKI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can reduce power supply impedance at an antiresonant frequency while keeping the power supply impedance at a resonant frequency low.SOLUTION: On a multilayer wiring board 1, an IC 50 and two multilayer ceramic capacitors (decoupling capacitors) 60, 67 connected in parallel with each other between a power source and a ground of the IC 50 are mounted. The two multilayer ceramic capacitors 60, 67 include the multilayer ceramic capacitor 67 connected by a wiring pattern 15 including a resistance pattern 16 having a predetermined resistance value and the multilayer ceramic capacitor 60 connected by a wiring pattern 14 not including the resistance pattern 16. An ESR of the multilayer ceramic capacitor 60 is set at 100 mΩ or less and combined resistance of an ESR and the resistance pattern 16 of the multilayer ceramic capacitor 67 is set at no fewer than 1.5 Ω nor more than 20 Ω.
摘要翻译：要解决的问题：提供一种能够在将电源阻抗保持在谐振频率低的同时降低反谐振频率下的电源阻抗的多层布线基板。解决方案：在多层布线板1上安装IC 50和在电源和IC 50的接地之间彼此并联连接的两个多层陶瓷电容器（去耦电容器）60,67。两层叠陶瓷电容器60,67包括由包括具有预定电阻值的电阻图案16的布线图案15连接的多层陶瓷电容器67，并且层叠陶瓷电容器60通过不包括电阻图案16的布线图案14连接。层叠陶瓷电容器60的ESR设定为100mΩ以下，并且层叠陶瓷电容器67的ESR和电阻图案16的组合电阻被设定为不低于1.5Ω，也不大于20Ω。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2015050384A 半導体装置有权
标题翻译：半导体器件
公开(公告)号：JP2015050384A
公开(公告)日：2015-03-16
申请号：JP2013182363
申请日：2013-09-03
申请人：ルネサスエレクトロニクス株式会社 , Renesas Electronics Corp
发明人： TAKAHASHI SATOSHI , KARIYAZAKI SHUICHI
IPC分类号： H01L23/12 , H01L23/02 , H01L25/00
CPC分类号： H01L23/04 , H01L21/50 , H01L23/3675 , H01L23/3736 , H01L23/49838 , H01L23/50 , H01L23/544 , H01L23/562 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/74 , H01L24/97 , H01L25/165 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/0401 , H01L2224/04042 , H01L2224/0913 , H01L2224/13101 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2224/92125 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/0132 , H01L2924/13091 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/19106 , H05K1/0266 , H05K3/3442 , H05K3/3489 , H05K2201/066 , H05K2201/09781 , H05K2201/1056 , H05K2201/10636 , H05K2203/0169 , H05K2203/0173 , H05K2203/167 , H05K2203/168 , Y02P70/611 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2924/014
摘要：【課題】配線基板に対する電子部品の搭載位置に誤差が生じることを抑制する。【解決手段】第1半導体チップSC1は、主面SFC3及び裏面SFC4を有している。裏面SFC4は、主面SFC3の反対側の面である。配線基板ISUBは矩形であり、主面SFC1及び裏面SFC2を有している。主面SFC1には、第1半導体チップSC1が搭載されている。リッドLIDは、配線基板ISUBの主面SFC1及び第1半導体チップSC1を覆う。電子部品ELP1は、配線基板ISUBの裏面SFC2に搭載されている。そして、配線基板ISUBの主面SFC1は、少なくとも互いに対向する2つの角に、リッドLIDに覆われていない非被覆領域を有している。【選択図】図2
摘要翻译：要解决的问题：抑制相对于布线板的电子部件安装位置的误差的发生。解决方案：半导体器件包括：具有主表面SFC3和后表面SFC4的第一半导体芯片SC1，其中后表面SFC4是与主表面SFC3相反的一侧的表面; 在第一半导体芯片SC1安装在主面SFC1上的具有矩形形状和主面SFC1和后面SFC2的布线板ISUB; 覆盖布线板ISUB的主面SFC1和第一半导体芯片SC1的盖子LID; 以及安装在布线板ISUB的背面SFC2上的电子部件ELP1。布线板ISUB的主表面SFC1至少在彼此相对的两个角上未被盖子LID覆盖的未覆盖区域。

8. 发明专利

JP2014096501A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014096501A
公开(公告)日：2014-05-22
申请号：JP2012247805
申请日：2012-11-09
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KARIYAZAKI SHUICHI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L2224/14133 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To achieve a high-speed operation and high reliability in flip-chip connection in a semiconductor device employing flip-chip connection.SOLUTION: A semiconductor device comprises: a protection film SRU which covers wiring in a top layer formed on a top face of a wiring board IS and has an opening SRO extending in a direction parallel with one side of the wiring board IS; a plurality of lead electrodes LE which are composed of a part of the wiring in the top layer, extend in a direction perpendicular to one side of the wiring board IS and exposed from the opening SRO; and a plurality of bump electrodes PB which are formed in an outer peripheral region which is a part of an inner side from an edge of a semiconductor chip SC and to which the plurality of lead electrodes LE are connected via a plurality of solders.
摘要翻译：要解决的问题：在采用倒装芯片连接的半导体器件中实现倒装芯片连接的高速操作和高可靠性。解决方案：半导体器件包括：保护膜SRU，其覆盖顶层上形成的布线布线板IS的顶面，并且具有在与布线板IS的一侧平行的方向上延伸的开口SRO; 由顶层的一部分布线构成的多个引线电极LE在与布线基板IS的一侧垂直的方向上延伸并从开口SRO露出; 以及多个凸起电极PB，其形成在作为从半导体芯片SC的边缘的内侧的一部分的外周区域中，并且多个引线电极LE经由多个焊料相连接。

9. 发明专利

JP2012054597A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012054597A
公开(公告)日：2012-03-15
申请号：JP2011243075
申请日：2011-11-07
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： HORIE MASANAO , KARIYAZAKI SHUICHI
IPC分类号： H01L23/02 , H01L23/10 , H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/16152 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a lid is adhered to a semiconductor package substrate on which a semiconductor element is mounted so as to cover the semiconductor element, which provides means for preventing lid removal due to adhesive failure and breakdown due to defective cooling.SOLUTION: A semiconductor device 9 comprises a lid 5 housing a semiconductor element 1 in a center part and including a recess 5b with an adhesive surface adhered to the semiconductor element 1 and a flange part 5a with an adhesive surface 3a adhered to a semiconductor package substrate 3 on an outer periphery of the recess 5b. The lid 5 is formed such that a relation between a depth d1(μm) from the adhesive surface of the flange part 5a to the adhesive surface of the recess 5b and a length d2(μm) obtained by addition of a height from the adhesive surface of the semiconductor package substrate 3 to which the flange part 5a is adhered to the adhesive surface of the semiconductor element 1 adhered to the recess 5b with a thickness of an adhesive 6a satisfies the equation 25 μm≤d2-d1≤300 μm. Accordingly, the semiconductor device 9 has a clearance of not less than 25 μm but not more than 300 μm between the semiconductor package substrate 3 and the flange part 5a of the lid 5.
摘要翻译：要解决的问题：提供一种半导体器件，其中盖子被附着到其上安装半导体元件的半导体封装基板上以覆盖半导体元件，该半导体器件提供用于防止由于粘合剂故障引起的盖子移除的装置并由于冷却不良导致故障。解决方案：半导体器件9包括将半导体元件1容纳在中心部分并且包括具有粘附到半导体元件1的粘合表面的凹部5b的盖5和具有粘附表面3a的粘合表面3a的凸缘部5a 半导体封装基板3在凹部5b的外周。盖5形成为从凸缘部分5a的粘合表面到凹部5b的粘合表面的深度d1（μm）与通过从粘合表面添加高度而获得的长度d2（μm）之间的关系对于半导体封装基板3，其中凸缘部分5a粘附到粘附到具有粘合剂6a的厚度的凹部5b的半导体元件1的粘合表面上，满足公式25μm≤d2-d1≤300μm。因此，半导体器件9在半导体封装基板3与盖5的凸缘部5a之间具有不小于25μm但不大于300μm的间隙。（C）2012，JPO＆INPIT

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