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1. 发明专利

JP2012164817A Multilayer wiring board 审中-公开
标题翻译：多层接线板
公开(公告)号：JP2012164817A
公开(公告)日：2012-08-30
申请号：JP2011024170
申请日：2011-02-07
申请人： Murata Mfg Co Ltd , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 株式会社村田製作所
发明人： YAMANAGA ISAO , ICHIMURA TAKASHI , AZUMA TAKAHIRO , AKIMOTO TETSUYA , KARIYAZAKI SHUICHI , SHIRAI WATARU , TSUKUDA TATSUAKI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can reduce power supply impedance at an antiresonant frequency while keeping the power supply impedance at a resonant frequency low.SOLUTION: Between a power source and a ground of an IC 50 mounted on a multilayer wiring board 1, one or more (two in Fig. 1) high ESR capacitors 70 each having an ESL of 1 nH or less and an ESR of no fewer than 1.5 Ω nor more than 20 Ω, and one or more (two in Fig. 1) low ESR capacitors 60 each having an ESL of 1 nH or less and an ESR of 100 mΩ or less are connected in parallel. The multilayer wiring board 1 can reduce impedance at an antiresonant frequency less than half (equivalent of -6 dB noise reduction) in comparison with the case provided with only low ESR capacitors 60, while keeping power supply impedance at a resonant frequency low.
摘要翻译：要解决的问题：提供一种能够在将电源阻抗保持在谐振频率低的同时降低反谐振频率下的电源阻抗的多层布线基板。解决方案：在安装在多层布线板1上的IC 50的电源和地之间，一个或多个（图1中的两个）高ESR电容器70各自具有1nH以下的ESL和ESR 不小于1.5Ω且不大于20Ω，并且并联连接一个或多个（图1中的两个）具有1nH以下的ESL和100mΩ以下的ESR的低ESR电容器60。与仅提供低ESR电容器60的情况相比，多层布线板1可以将谐振频率低的电源阻抗保持在小于半（相当于-6dB噪声降低）的反谐振频率处的阻抗。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012164816A Multilayer wiring board 审中-公开
标题翻译：多层接线板
公开(公告)号：JP2012164816A
公开(公告)日：2012-08-30
申请号：JP2011024169
申请日：2011-02-07
申请人： Murata Mfg Co Ltd , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 株式会社村田製作所
发明人： ICHIMURA TAKASHI , YAMANAGA ISAO , AZUMA TAKAHIRO , AKIMOTO TETSUYA , KARIYAZAKI SHUICHI , SHIRAI WATARU , TSUKUDA TATSUAKI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can reduce power supply impedance at an antiresonant frequency while keeping the power supply impedance at a resonant frequency low.SOLUTION: On a multilayer wiring board 1, an IC 50 and two multilayer ceramic capacitors (decoupling capacitors) 60, 67 connected in parallel with each other between a power source and a ground of the IC 50 are mounted. The two multilayer ceramic capacitors 60, 67 include the multilayer ceramic capacitor 67 connected by a wiring pattern 15 including a resistance pattern 16 having a predetermined resistance value and the multilayer ceramic capacitor 60 connected by a wiring pattern 14 not including the resistance pattern 16. An ESR of the multilayer ceramic capacitor 60 is set at 100 mΩ or less and combined resistance of an ESR and the resistance pattern 16 of the multilayer ceramic capacitor 67 is set at no fewer than 1.5 Ω nor more than 20 Ω.
摘要翻译：要解决的问题：提供一种能够在将电源阻抗保持在谐振频率低的同时降低反谐振频率下的电源阻抗的多层布线基板。解决方案：在多层布线板1上安装IC 50和在电源和IC 50的接地之间彼此并联连接的两个多层陶瓷电容器（去耦电容器）60,67。两层叠陶瓷电容器60,67包括由包括具有预定电阻值的电阻图案16的布线图案15连接的多层陶瓷电容器67，并且层叠陶瓷电容器60通过不包括电阻图案16的布线图案14连接。层叠陶瓷电容器60的ESR设定为100mΩ以下，并且层叠陶瓷电容器67的ESR和电阻图案16的组合电阻被设定为不低于1.5Ω，也不大于20Ω。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2006114801A Common mode choke coil 审中-公开
标题翻译：共用模式选择线圈
公开(公告)号：JP2006114801A
公开(公告)日：2006-04-27
申请号：JP2004302509
申请日：2004-10-18
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI , YAMANAGA ISAO
IPC分类号： H01F27/00 , H01C7/10 , H01F17/00 , H01F37/00 , H03H7/09
摘要： PROBLEM TO BE SOLVED: To provide a common choke coil that employs a distributed constant element structure for a varistor to prevent the characteristic impedance from lowering, and takes countermeasures against surges without distorting the waveform of a differential signal. SOLUTION: This common choke coil has the first and second external electrodes 3-1 and 3-2, and the third and fourth external electrodes 3-3 and 3-4 in a chip body 2. The chip body 2 has a structure where the second coil block 6 is laminated on the first coil block 4 via a static protection layer 5. Concretely, the insulated layers 41 and 42 and coil pattern 43 are laminated on a magnetic substrate 40 to form a first coil block 4, and the static protection layer 5 formed using the varistor materials is laminated on the insulated layer 42, covering the entire coil pattern 43. Then, the coil pattern 60, insulated layers 61 and 62, and magnetic substrate 63 are laminated on the static protection layer 5 to form the second coil block 6. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种采用用于变阻器的分布常数元件结构的公共扼流圈，以防止特性阻抗降低，并且对抗浪涌采取对策而不使差分信号的波形失真。解决方案：该公共扼流线圈在芯片体2中具有第一外部电极3-1和第二外部电极3-2以及第三和第四外部电极3-3和3-4。芯片体2具有通过静电保护层5将第二线圈块6层叠在第一线圈块4上的结构。具体地，将绝缘层41,42和线圈图案43层压在磁性基板40上，形成第一线圈块4，使用变阻器材料形成的静电保护层5层叠在绝缘层42上，覆盖整个线圈图案43.然后，将线圈图案60，绝缘层61和62以及磁性基板63层叠在静电保护层5上以形成第二线圈块6.版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2014045056A Mounting structure of mounting two-terminal capacitor on substrate 审中-公开
标题翻译：在基板上安装两端电容器的安装结构
公开(公告)号：JP2014045056A
公开(公告)日：2014-03-13
申请号：JP2012186184
申请日：2012-08-27
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： KANO JUN , YAMANAGA ISAO
IPC分类号： H05K9/00
摘要： PROBLEM TO BE SOLVED: To provide a mounting structure for mounting a two-terminal capacitor on a substrate which can deal with reduction in the size and profile of electronic components, while exhibiting the characteristics as a capacitor sufficiently.SOLUTION: A capacitor 11 is covered with a shield case 28 and mounted, as a bypass capacitor, on a circuit board 21 while standing vertically. A hot electrode 13a of the capacitor 11 is connected electrically, by soldering, with a hot conductor path 25 formed on the surface of the circuit board 21. A ground electrode 13b of the capacitor 11 is connected electrically with the inner wall of a shield case 28 located above the hot conductor path 25 connected with the hot electrode 13a electrically. This electrical connection is carried out by bonding the ground electrode 13b to the inner wall of a shield case 28 by means of a conductive adhesive 32, and fixing the ground electrode 13b in place.
摘要翻译：要解决的问题：提供一种用于在基板上安装两端电容器的安装结构，其可以充分地表现出作为电容器的特性的电子部件的尺寸和轮廓的减小。解决方案：电容器11被覆盖具有屏蔽壳28并作为旁路电容器安装在电路板21上，同时竖立地竖立。电容器11的热电极13a通过焊接与形成在电路板21的表面上的热导体路径25电连接。电容器11的接地电极13b与屏蔽壳体的内壁电连接 28位于与热电极13a电连接的热导体路径25上方。该电气连接是通过用导电性粘合剂32将接地电极13b与屏蔽壳体28的内壁接合，将接地电极13b固定在适当位置来进行的。

5. 发明专利

JP2008071821A Common mode choke coil 审中-公开
标题翻译：共用模式选择线圈
公开(公告)号：JP2008071821A
公开(公告)日：2008-03-27
申请号：JP2006247049
申请日：2006-09-12
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： KUDO KAZUHIDE , YAMANAGA ISAO , MATSUDA KATSUJI , KAWAGUCHI MASAHIKO
IPC分类号： H01F17/04 , H01F27/00 , H03H7/09
摘要： PROBLEM TO BE SOLVED: To provide a small-sized common mode choke coil for removing high frequency noise. SOLUTION: The common mode choke coil 1 is constituted by providing a laminated body 4 between a first magnetic substrate 2 and a second magnetic substrate 3. Moreover, the laminated body 4 is formed by laminating a first insulating layer 5, a primary coil 10, an inter-coil insulating layer 11, a secondary coil 16, and a second insulating layer 17 or the like. Thicknesses T1, T2 of the insulating layers 5, 17 are set to values equal to or larger than 12.5 μm. Accordingly, since a rate of an electric line of a force generated at the periphery of each coil 10, 16 passing the inside of each insulating layer 5, 17 increases, floating capacities of the coils 10, 16 can be reduced. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供用于去除高频噪声的小型共模扼流线圈。解决方案：共模扼流线圈1是通过在第一磁性基板2和第二磁性基板3之间设置层压体4来构成的。此外，层叠体4通过层叠第一绝缘层5，初级线圈10，线圈间绝缘层11，次级线圈16和第二绝缘层17等。将绝缘层5,17的厚度T1，T2设定为12.5μm以上的值。因此，由于在通过每个绝缘层5,17的内部的每个线圈10,166的周边处产生的力的电力线的速率增加，所以可以减小线圈10,16的浮动容量。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007173669A Multilayered circuit board and integrated circuit package 有权
标题翻译：多层电路板和集成电路封装
公开(公告)号：JP2007173669A
公开(公告)日：2007-07-05
申请号：JP2005371530
申请日：2005-12-26
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： YAMANAGA ISAO , AZUMA TAKAHIRO
IPC分类号： H01L25/00
CPC分类号： H01L2924/15159 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide a multilayered circuit board in which a capacitor having decoupling and bypass functions is mounted very close to an IC power terminal, thus preventing IC's malfunctions, and an IC package.
SOLUTION: The multilayered circuit board has an IC package 1, a signal layer 2, a ground layer 3, and a power supply layer 4. The IC package 1 has a terminal block of a ball grid array type and a recess 11. The signal layer 2 has a mounting space S1 for a 2-terminal capacitor 7. A land 21 corresponding to the power terminal 12 of the IC package 1, and a land 22 opposed to this land 21, are prepared in this mounting space S1. The 2-terminal capacitor 7 is connected to the lands 21 and 22. Consequently, the power terminal 12 is connected to the power supply layer 4 through the land 21 to which the 2-terminal capacitor 7 is connected and via-holes 41 to 43, and an earth terminal 72 of the 2-terminal capacitor 7 is connected to the ground layer 3 through the land 22 and a via-hole 31.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种其中具有去耦和旁路功能的电容器非常靠近IC电源端子安装的多层电路板，从而防止IC的故障和IC封装。解决方案：多层电路板具有IC封装1，信号层2，接地层3和电源层4.IC封装1具有球栅阵列型端子块和凹槽11 信号层2具有用于2端子电容器7的安装空间S1。在该安装空间S1中准备对应于IC封装1的电源端子12的焊盘21和与该焊盘21相对的焊盘22 。 2端子电容器7连接到焊盘21和22.因此，电源端子12通过连接2端子电容器7的焊盘21和通孔41至43连接到电源层4 ，并且2端子电容器7的接地端子72通过焊盘22和通孔31连接到接地层3上。（C）2007，JPO＆INPIT

7. 发明专利

JP2013161458A Method for setting bypass capacitor constant, bypass capacitor constant setting device, and bypass capacitor constant setting program 审中-公开
标题翻译：用于设置旁路电容器常数的方法，旁路电容器恒定设置装置和旁路电容器恒定设置程序
公开(公告)号：JP2013161458A
公开(公告)日：2013-08-19
申请号：JP2012025599
申请日：2012-02-08
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： YAMANAGA ISAO , ICHIMURA TAKASHI , AZUMA TAKAHIRO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a method for setting a bypass capacitor constant capable of decreasing a power supply impedance in antiresonant frequency while retaining the power supply impedance in resonant frequency low without changing a predetermined layout of a circuit board.SOLUTION: In a step S102, a substrate model of a multilayer circuit board 100 in which the arrangement of bypass capacitors 160 and 170 are determined is formed. A coupled model formed by coupling capacitor models of the bypass capacitors 160 and 170 whose ESRs (Equivalent Series Resistance) are unknown are adopted for the substrate model. In a step S104, as for the coupled model, the ESRs of the bypass capacitors 160 and 170 for optimizing a minimum value and a maximum value of the power supply impedance are investigated.
摘要翻译：要解决的问题：提供一种设置旁路电容器常数的方法，该旁路电容器常数能够降低反谐振频率中的电源阻抗，同时将电源阻抗保持在谐振频率低，而不改变电路板的预定布局。解决方案：在步骤 S102，形成了其中确定旁路电容器160和170的布置的多层电路板100的基板模型。对于衬底模型，采用由ESR（等效串联电阻）未知的旁路电容器160和170的电容器模型耦合形成的耦合模型。在步骤S104中，对于耦合模型，研究用于优化最小值和电源阻抗的最大值的旁路电容器160和170的ESR。

8. 发明专利

JP2006024772A Common mode noise filter 审中-公开
标题翻译：通用模式噪声滤波器
公开(公告)号：JP2006024772A
公开(公告)日：2006-01-26
申请号：JP2004201985
申请日：2004-07-08
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： YAMANAGA ISAO
IPC分类号： H01F30/00 , H01F17/00 , H03H7/09
摘要： PROBLEM TO BE SOLVED: To provide a common mode noise filter comprising symmetrical first and second coils of the same shape having a uniform characteristic impedance.
SOLUTION: There are provided the first and the second coils 1, 2 of nearly the same shape, insulating layers 3 including these coils 1 and 2, magnetic layers 4-1, 4-2 covering the insulating layers 3, and external electrodes 5-1 to 5-4. The center of the coil 2 is slightly eccentric from the coil 1 in the plane direction. More specifically, the paired line segments 10-1, 20-1, 10-2, 20-2 to 10-13, 20-13 of the first and the second coil bodies 10, 20 are provided in the first and the second layers 3-1, 3-2 of the insulating layers 3, and are connected in series via through holes 31a, 31a-37a, 37a. Further, a first and a second internal leads 12, 22 are juxtaposed on the third layer 3-3 of the insulating layers 3, and are connected to the coil bodies 10, 20 via through holes 37b, 37b.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种共模噪声滤波器，包括具有均匀特性阻抗的相同形状的对称的第一和第二线圈。解决方案：提供了几乎相同形状的第一和第二线圈1,2，包括这些线圈1和2的绝缘层3，覆盖绝缘层3的磁性层4-1,4-2和外部电极5-1〜5-4。线圈2的中心在平面方向上与线圈1稍微偏心。更具体地，第一和第二线圈体10,20的成对线段10-1,20-1,10-2,20-2至10-13,20-13设置在第一和第二层中绝缘层3的3-1,3-2，并且通过通孔31a，31a-37a，37a串联连接。此外，第一和第二内部引线12,22并置在绝缘层3的第三层3-3上，并且经由通孔37b，37b连接到线圈体10,20。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005218031A Transmission line type common-mode filter 审中-公开
标题翻译：传输线型共通滤波器
公开(公告)号：JP2005218031A
公开(公告)日：2005-08-11
申请号：JP2004025545
申请日：2004-02-02
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： YAMANAGA ISAO , HARADA TORU
IPC分类号： H03H7/09
摘要： PROBLEM TO BE SOLVED: To provide a transmission line type common-mode filter for improving transmission characteristic at the time of a normal mode operation while maintaining satisfactory noise suppression characteristic at the time of a common-mode operation even when applied to a system that adopts a differential unbalance transmission system.
SOLUTION: This transmission line type common-mode filter has a structure in which external electrodes 10-1 to 12-2 are attached outside a chip 2. The chip 2 has transmission liens 4-1 and 4-2 and ground electrodes 3-1 and 3-2. The transmission line 4-1 and the transmission line 4-2 consist of a signal line 41 and a ground line 43, and a signal line 42 and the ground line 43, respectively, sharing one ground line 43. The transmission lines 4-1 and 4-2 like this are covered with a dielectric 5 with a rectangular cross-section, and a magnetic body 6 is filled between the ground electrodes 3-1 and 3-2.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种传输线型共模滤波器，用于在正常模式操作时改善传输特性，同时在共模操作时保持令人满意的噪声抑制特性，即使应用于采用差动不平衡传动系统。解决方案：该传输线型共模滤波器具有将外部电极10-1至12-2安装在芯片2的外部的结构。芯片2具有发送留线4-1和4-2以及接地电极 3-1和3-2。传输线4-1和传输线4-2分别由信号线41和接地线43以及共用一条接地线43的信号线42和接地线43组成。传输线4-1 4-2被截面矩形的电介质5覆盖，在接地电极3-1,3-2之间填充有磁性体6。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2014099469A Multilayer capacitor and its mounting structure to substrate 审中-公开
标题翻译：多层电容器及其基片安装结构
公开(公告)号：JP2014099469A
公开(公告)日：2014-05-29
申请号：JP2012249514
申请日：2012-11-13
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： YAMANAGA ISAO , AZUMA TAKAHIRO
IPC分类号： H01G4/12 , H01G4/30
摘要： PROBLEM TO BE SOLVED: To provide a multilayer capacitor that allows avoiding risk of a short circuit between a hot external electrode and a ground external electrode, and to provide its mounting structure to a substrate.SOLUTION: In a capacitor 11, a pair of hot external electrodes 13a and 13b to which a voltage is applied and a ground external electrode 14 that is grounded are exposed outside the capacitor. The ground external electrode 14 is provided on one end surface of a ceramic element body 12, and the pair of hot external electrodes 13a and 13b are provided on the other end surface opposite to the one end surface. The capacitor 11 is covered with a shield case 31 on a circuit board 21. The shield case 31 is electrically connected to a circuit-board ground plane 23, and is electrically connected to the ground external electrode 14 by an elastic piece 31a. The pair of hot external electrodes 13a and 13b are electrically connected to power-supply lines 22a and 22b.
摘要翻译：要解决的问题：提供一种能够避免热外部电极和接地外部电极之间的短路风险的多层电容器，并将其安装结构提供给基板。解决方案：在电容器11中，一对热施加了电压的外部电极13a和13b以及接地的接地外部电极14暴露在电容器的外部。接地外部电极14设置在陶瓷元件主体12的一个端面上，并且一对热外部电极13a和13b设置在与该一个端面相对的另一端面上。电容器11被电路板21上的屏蔽壳体31覆盖。屏蔽壳体31与电路板接地面23电连接，并通过弹性片31a与接地外部电极14电连接。一对热外部电极13a和13b电连接到电源线22a和22b。

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