专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2012164817A Multilayer wiring board 审中-公开
标题翻译：多层接线板
公开(公告)号：JP2012164817A
公开(公告)日：2012-08-30
申请号：JP2011024170
申请日：2011-02-07
申请人： Murata Mfg Co Ltd , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 株式会社村田製作所
发明人： YAMANAGA ISAO , ICHIMURA TAKASHI , AZUMA TAKAHIRO , AKIMOTO TETSUYA , KARIYAZAKI SHUICHI , SHIRAI WATARU , TSUKUDA TATSUAKI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can reduce power supply impedance at an antiresonant frequency while keeping the power supply impedance at a resonant frequency low.SOLUTION: Between a power source and a ground of an IC 50 mounted on a multilayer wiring board 1, one or more (two in Fig. 1) high ESR capacitors 70 each having an ESL of 1 nH or less and an ESR of no fewer than 1.5 Ω nor more than 20 Ω, and one or more (two in Fig. 1) low ESR capacitors 60 each having an ESL of 1 nH or less and an ESR of 100 mΩ or less are connected in parallel. The multilayer wiring board 1 can reduce impedance at an antiresonant frequency less than half (equivalent of -6 dB noise reduction) in comparison with the case provided with only low ESR capacitors 60, while keeping power supply impedance at a resonant frequency low.
摘要翻译：要解决的问题：提供一种能够在将电源阻抗保持在谐振频率低的同时降低反谐振频率下的电源阻抗的多层布线基板。解决方案：在安装在多层布线板1上的IC 50的电源和地之间，一个或多个（图1中的两个）高ESR电容器70各自具有1nH以下的ESL和ESR 不小于1.5Ω且不大于20Ω，并且并联连接一个或多个（图1中的两个）具有1nH以下的ESL和100mΩ以下的ESR的低ESR电容器60。与仅提供低ESR电容器60的情况相比，多层布线板1可以将谐振频率低的电源阻抗保持在小于半（相当于-6dB噪声降低）的反谐振频率处的阻抗。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2014116371A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014116371A
公开(公告)日：2014-06-26
申请号：JP2012267653
申请日：2012-12-06
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： OKADA MAKOTO , KARIYAZAKI SHUICHI , SHIRAI WATARU , SUZUHARA MASAFUMI , SERA NAOKO
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L25/0655 , H01L23/02 , H01L23/04 , H01L23/055 , H01L23/28 , H01L23/498 , H01L23/49816 , H01L23/562 , H01L24/33 , H01L2224/16225 , H01L2224/32225 , H01L2224/3224 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2924/1015 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/16251 , H01L2924/167 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve such problems that a board having a wider area is required for achieving a semiconductor device including a plurality of semiconductor chips mounted on the same board, a semiconductor device tends to cause warpage and distortion when an area of a board is increased while suppressing an increase in thickness of the board, and mounting a semiconductor device on a wiring board becomes difficult and impossible when warpage and distortion are caused in the semiconductor device.SOLUTION: Warpage in a semiconductor device can be suppressed by mounting two semiconductor chips on the same diagonal line of a board and mounting one of the semiconductor chips on the intersection point of the two diagonal lines of the board.
摘要翻译：要解决的问题为了解决这样的问题：为了实现包括安装在同一板上的多个半导体芯片的半导体器件，需要具有较宽面积的电路板，当板的面积变化时，半导体器件趋于产生翘曲和变形在抑制板的厚度增加的同时增加，并且在半导体器件中引起翘曲和变形时，难以并且不可能将半导体器件安装在布线板上。解决方案：可以通过安装两个半导体来抑制半导体器件中的翘曲芯片在板的相同对角线上，并且在板的两条对角线的交点上安装半导体芯片之一。

3. 发明专利

JP2012164816A Multilayer wiring board 审中-公开
标题翻译：多层接线板
公开(公告)号：JP2012164816A
公开(公告)日：2012-08-30
申请号：JP2011024169
申请日：2011-02-07
申请人： Murata Mfg Co Ltd , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 株式会社村田製作所
发明人： ICHIMURA TAKASHI , YAMANAGA ISAO , AZUMA TAKAHIRO , AKIMOTO TETSUYA , KARIYAZAKI SHUICHI , SHIRAI WATARU , TSUKUDA TATSUAKI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can reduce power supply impedance at an antiresonant frequency while keeping the power supply impedance at a resonant frequency low.SOLUTION: On a multilayer wiring board 1, an IC 50 and two multilayer ceramic capacitors (decoupling capacitors) 60, 67 connected in parallel with each other between a power source and a ground of the IC 50 are mounted. The two multilayer ceramic capacitors 60, 67 include the multilayer ceramic capacitor 67 connected by a wiring pattern 15 including a resistance pattern 16 having a predetermined resistance value and the multilayer ceramic capacitor 60 connected by a wiring pattern 14 not including the resistance pattern 16. An ESR of the multilayer ceramic capacitor 60 is set at 100 mΩ or less and combined resistance of an ESR and the resistance pattern 16 of the multilayer ceramic capacitor 67 is set at no fewer than 1.5 Ω nor more than 20 Ω.
摘要翻译：要解决的问题：提供一种能够在将电源阻抗保持在谐振频率低的同时降低反谐振频率下的电源阻抗的多层布线基板。解决方案：在多层布线板1上安装IC 50和在电源和IC 50的接地之间彼此并联连接的两个多层陶瓷电容器（去耦电容器）60,67。两层叠陶瓷电容器60,67包括由包括具有预定电阻值的电阻图案16的布线图案15连接的多层陶瓷电容器67，并且层叠陶瓷电容器60通过不包括电阻图案16的布线图案14连接。层叠陶瓷电容器60的ESR设定为100mΩ以下，并且层叠陶瓷电容器67的ESR和电阻图案16的组合电阻被设定为不低于1.5Ω，也不大于20Ω。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2014099436A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2014099436A
公开(公告)日：2014-05-29
申请号：JP2012248943
申请日：2012-11-13
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SHIRAI WATARU , TSUCHIYA KEITA
IPC分类号： H01L23/12 , H01L23/14 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve the problem in a semiconductor integrated circuit device, such as a flip-chip connected BGA, in which a semiconductor chip is flip-chip connected on an organic multilayer wiring board as an interposer, that although a non-fusing type bump electrode, such as a copper pillar, is used to reduce the bump pitch of the flip-chip connection, a flip-chip connected BGA, etc. using this non-fusing type bump electrode tends to cause a separation or crack to occur in a wiring interlayer film of the semiconductor chip.SOLUTION: The present invention is to ensure that, in a semiconductor integrated circuit device such as a flip-chip connected BGA using, as an interposer, a multilayer build-up board having an organic core board, a copper pillar is disposed so that its position does not overlap, in a plane view, a buried via penetrating the organic core board.
摘要翻译：要解决的问题为了解决半导体集成电路器件中的问题，例如半导体芯片连接的BGA，其中半导体芯片以倒装芯片连接在作为插入器的有机多层布线板上，使用诸如铜柱的熔合型凸起电极来减小倒装芯片连接的凸起间距，使用该非熔合型凸块电极的倒装芯片连接的BGA等，往往会导致分离或破裂发生在半导体芯片的布线层间膜中。解决方案：本发明是为了确保在半导体集成电路器件如倒装芯片连接的BGA中使用具有有机物的多层叠层板作为插入件核心板，铜柱被布置成使得其位置在平面图中不重叠穿过有机芯板的埋入通孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式