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61. 发明专利

JPS5764949A Continous processor 失效
标题翻译：连续处理器
公开(公告)号：JPS5764949A
公开(公告)日：1982-04-20
申请号：JP14045480
申请日：1980-10-09
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd
发明人： NANKOU SUSUMU , MAEJIMA HIROSHI , NOMURA KEIZOU , ISHIOKA MASATO
IPC分类号： H01L21/30 , H01L21/00 , H01L21/027 , H01L21/677 , H01L21/68
CPC分类号： H01L21/67276 , H01L21/67259 , H01L21/68
摘要： PURPOSE:To continously perform the different processings of a processing index by providing a stocker before a stopping position temporarily and accommodating tentatively a work. CONSTITUTION:A wafer 2 is fed to a photosensitive processor 1, is then processed, and is thereafter fed to a stocker 6. Four belt conveyors 7 are sequentially moved, the wafer 2 is temporarily stopped at the end of a conveyor 5 and when a vacant is produced at a development processor 3, the wafer 2 is automatically fed to the processor 3. After the wafer is processed, it is fed to the next step. The existence or absence of the wafer is detected by a pair of light emitting unit and photodetector in each belt conveyor 7 and the conveyor 5 of the stocker, and the information is fed to a mechanism. Since this configuration has a preliminary wafer, the processor 3 is not stopped even if the processor 1 is temporarily stopped to clean and exchange the mask. Since the processor 3 is slow in the processing index but the wafer 2 is contained in the stocker 6, the processor 1 is continously operated without stoppage.
摘要翻译：目的：通过临时提供储存者暂时停止处理工作指标，并暂时适应工作，持续执行加工指标的不同处理。构成：晶片2被馈送到光敏处理器1，然后被处理，然后被供给到储料器6.四个带式输送机7依次移动，晶片2在传送带5的端部暂时停止，并且当一个在显影处理器3处产生空白，晶片2被自动馈送到处理器3.在处理晶片之后，将其馈送到下一步骤。每个带式输送机7和储料器的输送机5中的一对发光单元和光电检测器检测晶片的存在或不存在，并将信息馈送到机构。由于该配置具有初步晶片，即使处理器1暂时停止以清洁和更换掩模，处理器3也不会停止。由于处理器3处理索引较慢，而晶片2被包含在储存器6中，所以处理器1不间断地运行。

62. 发明专利

JP2004140139A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2004140139A
公开(公告)日：2004-05-13
申请号：JP2002302690
申请日：2002-10-17
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： GOTOU KUNIAKI
IPC分类号： H01L21/60 , H01L21/52
CPC分类号： H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To effect face-up type mounting and face-down type mounting by one set of chip mounter device, in a die bonding process for bonding a chip to a frame.
SOLUTION: The chip mounter device is provided with a die converting stage 9 having a mechanism for converting the front side and the rear side of a semiconductor chip 2 while the face-down type mount wherein the main surface of the semiconductor chip 2 is contacted with and bonded to the chip mounting region of a frame 13 and the face-up type mount wherein the rear side of the semiconductor chip 2 is contacted with and bonded to the chip mounting region of the frame 13 are effected by switching the converting mechanism of the die converting stage 9.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过一组芯片安装装置进行面朝上安装和面朝下安装，用于将芯片接合到框架的芯片接合工艺中。解决方案：芯片安装器装置设置有具有用于转换半导体芯片2的正面和背面的机构的模具转换台9，同时面向下型安装件，其中半导体芯片2的主表面与框架13的芯片安装区域接触并结合到框架13的芯片安装区域，并且半导体芯片2的后侧与框架13的芯片安装区域接合并结合到框架13的面朝上型安装件通过切换转换模具转换阶段的机制9.版权所有（C）2004，JPO

63. 发明专利

JP2004134591A Method for manufacturing semiconductor integrated circuit device 审中-公开
公开(公告)号：JP2004134591A
公开(公告)日：2004-04-30
申请号：JP2002297820
申请日：2002-10-10
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： KURATOMI BUNJI , SHIMIZU FUKUMI
IPC分类号： B29C45/34 , B29L31/34 , H01L21/44 , H01L21/56 , H01L21/98 , H01L23/31 , H01L25/065
CPC分类号： H01L25/50 , H01L21/565 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2225/06562 , H01L2225/06582 , H01L2924/01057 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To make depth of air vents constant irrespective of thickness of a substrate, to prevent non-filling of resin in a cavity, resin leakage or a weld defect, and to improve yield of a product in resin forming of a semiconductor integrated circuit device using the substrate. SOLUTION: In manufacture of the semiconductor integrated circuit device, a forming mold 6 is used which has a plurality of the air vents 7c and in which a movable pin 1 where a groove 1a is formed at a tip is installed to protrude to respective air bents 7c, and the tip of the movable pin 1 is pushed to a multi-cavity substrate 40 at the time of mold clamping. Thus, depths of the respective air vents 7c are made constant irrespective of dispersion of thickness of the multi-cavity substrate 40, and the cavity is filled with resin while air in the cavity is set free through the groove 1a at the tip of the movable pin 1. Thus, non-filling of resin in the cavity, occurrence of resin leakage or the weld defect can be prevented, and yield of the product can be improved. COPYRIGHT: (C)2004,JPO

64. 发明专利

JP2004104046A Semiconductor device and method for manufacturing the same 审中-公开
公开(公告)号：JP2004104046A
公开(公告)日：2004-04-02
申请号：JP2002267601
申请日：2002-09-13
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： MURAKAMI FUMIO
IPC分类号： B21D28/00 , H01L23/50
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the peeling at the time of dicing of the half etching part of the tie bar of a one-sided mold type package and a sealing resin. SOLUTION: A half etching part is arranged at the back side of a tie bar 20a part of a lead frame 20 to be used by a one-sided mold type package such as a QFN. A recessed part 41 is formed by half etching at the half etching part. In a state that the recessed part 41 is formed, the sealing resin 30 is arranged at the half etching part of the tie bar 20a. The recessed part 41 is made to function as a peeling resistance part 40. At the time of integrating multiple lead frames 20 into pieces, the peeling of the sealing resin 30 and the half etching part of the tie bar 20a can be prevented even at the time of cutting the tie bar 20a by a punching means or the like. COPYRIGHT: (C)2004,JPO

65. 发明专利

JP2003347319A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003347319A
公开(公告)日：2003-12-05
申请号：JP2002151300
申请日：2002-05-24
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： HOSONO AKISHI , MAKI HIROSHI
IPC分类号： H01L21/52 , H01L21/50
CPC分类号： H01L24/97 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/181 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent a nondefective semiconductor chip from being mounted on a defective die pad of a frame. SOLUTION: A bar code 5 corresponding to an ID number of a lead frame 1 is provided on the lead frame used for manufacturing a semiconductor device. The lead frame 1 is tested to detect defects of the die pads 2 and stores the position coordinate information of the defective die pad in a storage medium corresponding to the ID number of the lead frame 1. Before a die bonding process, the ID number of the lead frame 1 is read out of the bar code 5 of the lead frame 1 by a bar code reader 6, and then the position coordinate information of the defective die pad corresponding to the ID number of the lead frame 1 is read out of the storage medium, so that a die bonding process and a subsequent manufacturing process are performed by utilizing the position coordinate information of the defective die pad that has been read out. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了防止无缺陷的半导体芯片安装在框架的有缺陷的芯片焊盘上。解决方案：在用于制造半导体器件的引线框架上设置与引线框架1的ID号对应的条形码5。对引线框架1进行测试以检测管芯焊盘2的缺陷，并将缺陷管芯焊盘的位置坐标信息存储在与引线框1的ID号相对应的存储介质中。在管芯接合处理之前，通过条形码阅读器6从引线框架1的条形码5读出引线框1，然后从引线框1的ID号对应的缺陷管芯焊盘的位置坐标信息被读出存储介质，从而通过利用已经读出的有缺陷的管芯焊盘的位置坐标信息来执行管芯接合工艺和随后的制造工艺。版权所有（C）2004，JPO

66. 发明专利

JP2003068772A Method for die bonding and manufacturing method for semiconductor device 有权
标题翻译：用于半导体器件的DIE结合和制造方法的方法
公开(公告)号：JP2003068772A
公开(公告)日：2003-03-07
申请号：JP2001253204
申请日：2001-08-23
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所
发明人： TAKANO RYUICHI , MAKI HIROSHI , HASEBE ARIHIRO
IPC分类号： H01L21/677 , H01L21/52 , H01L21/67 , H01L21/68
摘要： PROBLEM TO BE SOLVED: To reduce a required time and labor, and improve adjusting accuracy in a bonding tool for a pick-up operation and a positioning operation for a pick-up tool. SOLUTION: After a specific die 51 on an adhesive tape 11 is picked up by a collet 40 supported with a bonding head through a supporting shaft 41, the die is returned to the original position on the adhesive tape 11. And then, the attaching error of the collet 40 on the bonding head is automatically detected based on the displacement between a die position (x1, y1, θ1) before the pick-up and a die position (x2, y2, θ2) after the pick-up. While the attaching error of the collet 40 is automatically compensated based on the error, the die-bonding by a direct pick-up method using the collet 40 is performed.
摘要翻译：要解决的问题：为了减少所需的时间和人力，并提高用于拾取操作的接合工具和拾取工具的定位操作的调节精度。解决方案：在通过支撑轴41由粘合头支撑的夹头40拾取粘合带11上的特定模具51之后，将模具返回到胶带11上的原始位置。然后，附着误差基于拾取前的模具位置（x1，y1，θ1）和拾取后的模具位置（x2，y2，θ2）之间的位移自动地检测粘合头上的夹头40的位置。虽然基于误差自动补偿夹头40的附着误差，但是通过使用夹头40的直接拾取方法进行芯片接合。

67. 发明专利

JP2003017652A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2003017652A
公开(公告)日：2003-01-17
申请号：JP2001195803
申请日：2001-06-28
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , Hitachi Ulsi Systems Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KANEDA TAKESHI , ONO HIROSHI , NISHIDA TAKAFUMI , ARITA JUNICHI , SHIBAMOTO MASAKUNI , SUZUKI KAZUNARI , MIYAZAKI CHUICHI , ARAO OSAMU
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2224/97 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device realizing high reliability with simple constitution.
SOLUTION: A second semiconductor chip is mounted on with the underside thereof being joined to the main surface of a first semiconductor chip, the first semiconductor chip is mounted on with the underside thereof being joined to a substrate, a protecting film is formed on the whole surface of the first semiconductor chip except a bonding electrode part, and the first and the second semiconductor chips and wiring means of the substrate are connected by wire bonding.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种以简单结构实现高可靠性的半导体器件。解决方案：第二半导体芯片安装在其下侧，与第一半导体芯片的主表面接合，第一半导体芯片安装在其下侧与基板相连，保护膜整体上形成除了接合电极部分之外的第一半导体芯片的表面以及基板的第一和第二半导体芯片和布线装置通过引线接合连接。

68. 发明专利

JP2000077393A Plasma processing system 审中-公开
标题翻译：等离子体处理系统
公开(公告)号：JP2000077393A
公开(公告)日：2000-03-14
申请号：JP24928998
申请日：1998-09-03
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所
发明人： IKEGAWA MASATO , TAMAI TAKAHIRO
IPC分类号： H01L21/302 , C23C16/50 , C23C16/509 , C23F4/00 , H01L21/205 , H01L21/3065 , H05H1/46
摘要： PROBLEM TO BE SOLVED: To make uniform an etching rate, an etching shape and a selection ratio in a substrate by arranging a ring higher than the substrate on the outer circumference thereof and applying a bias voltage to the ring thereby lowering the concentration of radicals generated in the vicinity of the outer circumference of the substrate.
SOLUTION: A substrate 4 is mounted on an electrode 3 disposed oppositely to an electrode 2 coupled with a chamber 1 and a ring 10 is disposed on the outside of the substrate 4. Consequently, CF based radicals and reaction products stand in the ring 10 and the quantity thereof impinging on the substrate 4 becomes uniform. When a bias power is applied to the ring 10, F radicals formed on the outside of the substrate 4 are consumed by the ring 10, concentration is increased on the outer circumference of the substrate 4 and the quantity of F radicals becomes uniform. Quantity of CF based radicals, F radicals and reaction products impinging onto the substrate 4 is made uniform in the plane thereof through combination of these effects.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了使衬底中的蚀刻速度，蚀刻形状和选择比均匀，通过在其外圆周上布置高于衬底的环并向环施加偏置电压，从而降低产生的自由基的浓度在基板的外周附近。解决方案：将基板4安装在与与腔室1连接的电极2相对设置的电极3上，并且环10设置在基板4的外侧。因此，基于CF的自由基和反应产物站在环10中，撞击在基板4上的数量变得均匀。当向环10施加偏置功率时，形成在基板4的外侧的F自由基被环10消耗，在基板4的外周上的浓度增加，并且F自由基的量变得均匀。通过这些效果的组合，冲击到基板4上的CF基自由基，F自由基和反应产物的数量在其平面内均匀。

69. 发明专利

JPS61124920A Lighting device 失效
标题翻译：照明设备
公开(公告)号：JPS61124920A
公开(公告)日：1986-06-12
申请号：JP24592684
申请日：1984-11-22
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd
发明人： KOMABA YUICHI , TANIMOTO MICHIO , OZAWA MASAKAZU , TAKASHIMA KAZUHISA , KONO TETSUYA
IPC分类号： H01L21/66 , G02B27/00
摘要： PURPOSE: To switch top lighting and slanting lighting according to the state of a surface to be lighted by allowing a top lighting system and a slanting lighting system to face a single light source, and providing the light source with a switching means which switches the projection of the light source upon both lighting systems.
CONSTITUTION: A reflecting mirror 7 is so supported as to revolve around the light source 6 under the control of a proper driving means such as a motor 8, thereby varying the projection direction of the light source 6. The top lighting system 9 and slanting lighting system 10 are arranged on two right-angled side walls of a dark box 5 respectively and both lighting systems 9 and 10 are composed of optical waveguide formed of a bundle of many optical fibers, lenses, etc. When the top lighting is performed, the direction of the reflecting mirror 7 is so controlled that light from the light source 6 is projected on only the top lighting system 9, and the light incident on the top lighting system 9 is guided to illuminate a half-mirror 3 from its terminal. When the slanting lighting is performed, the direction of the reflecting mirror 7 is changed by a servomotor 8 so as to project the light from the light source 6 on only the slanting light source 10.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过允许顶部照明系统和倾斜照明系统面对单个光源，根据待点亮的表面的状态来切换顶部照明和倾斜照明，并为光源提供切换装置，其切换投影在两个照明系统上的光源。构成：在诸如马达8的适当的驱动装置的控制下，反射镜7被支撑为围绕光源6旋转，从而改变光源6的投射方向。顶部照明系统9和倾斜照明系统10分别布置在暗箱5的两个直角侧壁上，并且两个照明系统9和10由由许多光纤束，透镜等组成的光波导构成。当执行顶部照明时，反射镜7的方向受到控制，使得来自光源6的光仅投射在顶部照明系统9上，并且引导入射在顶部照明系统9上的光从其端子照射半反射镜3。当执行倾斜照明时，反射镜7的方向由伺服电动机8改变，以使来自光源6的光只投射在倾斜光源10上。

70. 发明专利

JPS61101044A Semiconductor device, manufacture thereof and exposing device to be used thereon 失效
标题翻译：半导体器件，其制造及其使用的裸露器件
公开(公告)号：JPS61101044A
公开(公告)日：1986-05-19
申请号：JP22217984
申请日：1984-10-24
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd
发明人： MUNAKATA HIROSHI
IPC分类号： H01L21/30 , G03F7/20 , H01L21/027 , H01L21/60 , H01L21/768 , H01L23/522
CPC分类号： H01L24/82 , H01L2224/24 , H01L2224/24225 , H01L2224/24226 , H01L2224/73267 , H01L2924/01004 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/00012
摘要： PURPOSE:To reduce the area of bonding and to perform a high density wiring by a method wherein each electrode pad of a pellet and each lead are electrically connected by a wiring in which a conductive film is provided by engraving in the prescribed form. CONSTITUTION:A pellet 2 whereon a plurality of electrode pads 3 are arranged on the circumferential part is bonded on an insulative base 1. A plurality of leads 4 whereon a pin 5 is connected are formed on the base 1. An insulating film 6 is formed on the base 1, and through hole conductors 7 and 8 are formed on the prescribed part of the insulating film 6. A plurality of wiring 9 is formed on the insulating film 6 in such a manner that it is connected to the conductors 7 and 8. Moreover, a protective film 10 is formed on the insulating film 6. As a result, a high density wiring can be accomplished by connecting the pads 3 and the leads 4 using the conductors 7 and 8 as above-mentioned.
摘要翻译：目的：为了减少接合面积，通过以规定的形式通过雕刻设置导电膜的布线将每个引线的每个电极焊盘电连接的方法来减小接合面积并进行高密度布线。构成：在圆周部分上布置多个电极焊盘3的颗粒2接合在绝缘基体1上。在基座1上形成有连接针5的多个引线4.形成绝缘膜6 在绝缘膜6的规定部分上形成有通孔导体7,8。在绝缘膜6上形成多个配线9，使其与导体7,8连接此外，在绝缘膜6上形成保护膜10.结果，如上所述，可以通过使用导体7和8连接焊盘3和引线4来实现高密度布线。

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