专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2004134443A Method of manufacturing semiconductor device 审中-公开
公开(公告)号：JP2004134443A
公开(公告)日：2004-04-30
申请号：JP2002294803
申请日：2002-10-08
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： TATE MITSUAKI , TSUCHIYA KUNIHIRO , HIGUCHI KAZUNORI , MOCHIZUKI TAKETO
IPC分类号： H01L23/12 , H01L21/52 , H01L21/60
CPC分类号： H01L2224/50
摘要： PROBLEM TO BE SOLVED: To provide a technology by which the index of a flip chip bonder can be improved. SOLUTION: The mean value of the deviation of a semiconductor chip 5 is calculated by performing chip bonding by an appointed number of times by correcting the positions of the chip 5 and a wiring board 3 based on the deviation of the chip 5 obtained by using an upper visual field recognizing camera 2d 2 , and that of the board 3 obtained by using a lower visual field recognizing camera 2d 1 . At the same time, sampling of the deviation of the chip 5 is performed. Thereafter, chip bonding is performed by correcting the positions of the chip 5 and board 3 based on the mean value of the deviation of the chip 5 and the deviation of the board 3 obtained by using the camera 2d 1 . COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004072037A Method for manufacturing semiconductor device 审中-公开
公开(公告)号：JP2004072037A
公开(公告)日：2004-03-04
申请号：JP2002232869
申请日：2002-08-09
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： MAKI HIROSHI , WADA EIJI
IPC分类号： H01L21/67 , H01L21/301 , H01L21/50 , H01L21/52 , H01L21/68
CPC分类号： H01L2221/68322
摘要： PROBLEM TO BE SOLVED: To provide a technique for bonding a semiconductor wafer to a thermal release tape as an adhesive sheet, cutting off the wafer bonded to the adhesive sheet into individual semiconductor chips, and accurately picking up the individual chips. SOLUTION: A vacuum member 5 is arranged under the semiconductor chip 2A to be picked up to suck the wafer sheet 1 bonded to the rear surface of the chip 2A. After the position of the chip 2A to be picked up is recognized, a heat block 6 for individually heating the chip is moved up to come into contact with the wafer sheet 1, and heats the chip 2A from its rear side. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2004063858A Method for manufacturing semiconductor device 审中-公开
公开(公告)号：JP2004063858A
公开(公告)日：2004-02-26
申请号：JP2002221068
申请日：2002-07-30
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： FUKADA HIROSHI , SUZUKI MASAKI , MITSUI KATSUHIRO , ONO DAISUKE
IPC分类号： B24B57/02 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To enable elimination of undesired substances, such as flocculated abrasive particles and scrap, without using a filter, when reusing slurry. SOLUTION: Used slurry discharged from polishing equipment, like CMP equipment, is subjected to recycling by concentration adjusting treatment, particle size adjustment treatment and PH adjusting treatment. In the particle size adjusting treatment, treatment is performed by a particle size adjustment treating part 32, which is provided with a flocculated adhesive particle crushing treatment part 40 by ultrasonic irradiation treatment or the like, a temperature separating treatment part 50, wherein flocculated adhesive particles etc. are separated from normal abrasive particles by controlling the slurry at nonuniform temperature, and a flocculated adhesive particle discarding part 60, wherein discarding treatment of separated flocculated adhesive particles etc. is performed. As a result, undesired substances like the abrasive particles is separated from the used slurry without using a filter, and slurry containing adhesive particles whose particle size is normal is collected. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2004039802A Method of manufacturing semiconductor device, and semiconductor manufacturing apparatus 审中-公开
公开(公告)号：JP2004039802A
公开(公告)日：2004-02-05
申请号：JP2002193532
申请日：2002-07-02
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： KURODA AKIRA , ISHIDA JUNICHI , SUDA TOMIJI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To suppress the misregistration due to thermal distortion during bonding, when bonding a semiconductor chip on a flexible wiring board formed out of a film material or the like.
SOLUTION: The flexible wiring board such as a film wiring board 20a is heated or heated and thrusted to be thermally expanded in advance. A slackness coming from the thermal expansion is removed by pushing down a bonding tool 15a. After removal of the slackness, a camera 16a for positional recognition is located between the film wiring board 20a and a semiconductor chip 30 to recognize the positions of the film wiring board 20a and the semiconductor chip 30, and to make positional adjustments based on the recognition results for a very precise alignment between the film wiring board 20a and the semiconductor chip 30. By carrying out bonding after the alignment, the misregistration due to heat during bonding can be suppressed.
COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2003347229A Method of manufacturing semiconductor device and semiconductor device 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：JP2003347229A
公开(公告)日：2003-12-05
申请号：JP2002158608
申请日：2002-05-31
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： KONDO TAIICHI , HIRASAWA WATARU , SUGII NOBUYUKI
IPC分类号： C23C16/42 , C23C16/44 , C23C16/455 , C30B25/00 , H01L21/20 , H01L21/205 , H01L29/78
CPC分类号： C23C16/45506 , C23C16/22 , C23C16/45523 , C23C16/45563 , C23C16/45578 , C23C16/4584 , C23C16/46 , C30B25/00 , C30B25/02 , C30B29/403 , C30B29/52 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/2807 , H01L29/1054 , H01L29/66575 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To shorten the forming time of a silicon-germanium film, and at the same time, to make the thickness and quality of the film uniform. SOLUTION: In a treatment chamber 2 of a batch CVD film forming device, the turbulent flow of film forming gas is generated by introducing the gas into the chamber 2 through a plurality of holes 7 formed in a gas nozzle 7. Then the silicon-germanium film is epitaxially grown on a semiconductor wafer 12 disposed in the chamber 2 in a state that pressure in the chamber 2 is adjusted to normal or quasi-normal pressure. After the silicon-germanium film is grown, a strained silicon film is epitaxially grown on the film. Thereafter, a semiconductor element is formed on the semiconductor wafer 12 on which the silicon-germanium film and a strained silicon film are formed. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：缩短硅 - 锗膜的形成时间，同时使膜的厚度和质量均匀。解决方案：在分批CVD膜形成装置的处理室2中，通过在气体喷嘴7中形成的多个孔7将气体引入室2而产生成膜气体的湍流。然后，在室2中的压力被调节到正常或准正常压力的状态下，在设置在室2中的半导体晶片12上外延生长硅 - 锗膜。在硅锗膜生长之后，在膜上外延生长应变硅膜。此后，在其上形成硅 - 锗膜和应变硅膜的半导体晶片12上形成半导体元件。版权所有（C）2004，JPO

6. 发明专利

JP2003332387A Bonding device and method for manufacturing semiconductor device 有权
标题翻译：用于制造半导体器件的接合器件和方法
公开(公告)号：JP2003332387A
公开(公告)日：2003-11-21
申请号：JP2002133913
申请日：2002-05-09
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： OKUBO TATSUYUKI , NADAMOTO KEISUKE
IPC分类号： H01L21/60
CPC分类号： H01L2224/50
摘要： PROBLEM TO BE SOLVED: To prevent extensive occurrence of failure bonding in single point lead bonding process. SOLUTION: In the inner lead bonding of a bonding object 5 where a chip 13 is held by a tape 16 having an inner lead 15 through an elastomer 14, a decision is made whether or not the height h2 of a bonding tool 4 when one inner lead 15 is grounded while pressing against a bonding pad 17 of the chip 13 exceeds the upper limit height h1 on the grounding face, i.e., the sum of thickness of the chip 13 and the inner lead 15 plus a specified allowance Δh. If the h2 exceeds the h1 due to presence of a foreign matter 300 on the back of a stage 6 and the chip 13, an alarm is delivered in order to inform occurrence of an error and bonding is interrupted thus preventing extensive occurrence of failure due to presence of a foreign matter 300, or the like. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了防止在单点引线接合工艺中大量发生故障接合。解决方案：在通过弹性体14的具有内引线15的带16保持芯片13的接合物体5的内引线接合中，判定接合工具4的高度h2 当一个内引线15被接地而按压芯片13的接合焊盘17时，超过接地面上的上限高度h1，即芯片13和内引线15的厚度之和加上规定的余量Δh。如果由于在载物台6和芯片13的背面存在异物300而导致的h2超过h1，则为了通知发生错误而发出报警，因此中断接合，从而防止由于异物300的存在等。版权所有（C）2004，JPO

7. 发明专利

JP2003332359A Method for manufacturing semiconductor device and semiconductor manufacturing apparatus 审中-公开
标题翻译：制造半导体器件和半导体制造设备的方法
公开(公告)号：JP2003332359A
公开(公告)日：2003-11-21
申请号：JP2002139415
申请日：2002-05-15
申请人： Hitachi Tokyo Electronics Co Ltd , Renesas Technology Corp , 日立東京エレクトロニクス株式会社 , 株式会社ルネサステクノロジ
发明人： FUKAZAWA HARUHIKO , MAKITA YOSHIAKI , MOCHIZUKI MASAYUKI
IPC分类号： H01L21/50
摘要： PROBLEM TO BE SOLVED: To rapidly change setting of waiting positions of an upper claw and a lower claw corresponding to the thickness of a work, in a grip mechanism used for conveying a work.
SOLUTION: Waiting position contacts P1, P2 for a pair of upper claw and lower claw to be opened or closed by a cam mechanism are set on a large diameter vertex and on the small diameter vertex of a cam 21a for the upper claw. When the work is thick, the upper claw is made to wait at the waiting position contact for the upper claw set to the large diameter vertex; while when the work is thin, the waiting position contact P2 for the upper claw set to the small diameter vertex is waited so that the upper claw can be opened or closed at the gripping time of the shortest upper claw stroke, in response to the thickness of the work.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：在用于输送作业的夹持机构中，快速地改变与工件的厚度对应的上爪和下爪的等待位置的设定。解决方案：用于由一凸轮机构打开或关闭的一对上爪和下爪的等待位置触点P1，P2设置在大直径的顶点上，并且在上爪的凸轮21a的小直径顶点上。当工作厚度大时，使上爪等待在与大直径顶点设置的上爪的等待位置接触处; 而当工作较薄时，等待设置为小直径顶点的上爪的等待位置接触P2，以便在最短的上爪行程的夹紧时间响应于厚度可以打开或关闭上爪的工作。版权所有（C）2004，JPO

8. 发明专利

JP2003273031A Method of manufacturing semiconductor device and semiconductor manufacturing method 审中-公开
标题翻译：制造半导体器件和半导体制造方法
公开(公告)号：JP2003273031A
公开(公告)日：2003-09-26
申请号：JP2002075362
申请日：2002-03-19
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所
发明人： AOKI TADASHI
IPC分类号： C23C16/44 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a technology for preventing reactive by-products adhered to the inside of a pressure gauge and a pressure gauge fitting pipe, which are fitted to a CVD system.
SOLUTION: An insulating film, a semiconductor film or a metal conductor film are deposited on a substrate by using the CVD system. Residual produced gas 14, remaining inside the pressure gauge and the pressure gauge fitting pipe 11, is evacuated by an evacuation vent pipe 13, whose one end is connected to the pressure gauge fitting pipe 11 and other end is connected to an exhaust pipe 4 connected to a vacuum pump 8 from a reaction chamber 1.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种技术，用于防止粘附在压力计内的反应性副产物和压力计配合管，其安装在CVD系统上。解决方案：通过使用CVD系统将绝缘膜，半导体膜或金属导体膜沉积在基板上。残留在压力计和压力表配管11内的残留气体14被排气通气管13排出，排气管13的一端连接到压力计配管11，另一端与连接的排气管4连接从反应室1到真空泵8.版权所有（C）2003，JPO

9. 发明专利

JP2003077965A Inspection apparatus for semiconductor device and method of inspecting semiconductor device using same 审中-公开
标题翻译：用于半导体器件的检查装置及使用其检查半导体器件的方法
公开(公告)号：JP2003077965A
公开(公告)日：2003-03-14
申请号：JP2001266731
申请日：2001-09-04
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , Hitachi Ulsi Systems Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： BAN KAZUHIRO , NEZU YUICHI , KAWAKAMI KENJI , FUJIKI NAOTO , YAMAGAMI TAKASHI , NAGAKURA TSUTOMU , AMARI HIROYUKI , SUGIYAMA YUKINORI
IPC分类号： G01R31/26 , G01R1/073 , G01R31/28 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a probing technique for preventing a short circuit caused when wiring contacts a semiconductor chip while securing strength of beams.
SOLUTION: A plurality of beams 11 in a double-supported-beam structure are placed in parallel on a wafer. A projection 12 is formed in the center of each beam 11 of the wafer. The projection 12 is coated with a metal film 13 as a contactor, and an electrode is formed for connection to the other side of the wafer. Wiring 14 for connecting the contactor and electrode derives the metal film 13 coated on the projection 12 from one side through the side of the beam 11 to the other side of the beam, where the wiring extends to connect the contractor and electrode, thus wiring does not extend on a surface to be inspected and the short circuit is prevented. Furthermore, the double- supported-beam structure of the beam 11 provides sufficient strength.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种用于防止当布线在确保梁的强度时接触半导体芯片时引起的短路的探测技术。解决方案：双支撑梁结构中的多个梁11平行放置在晶片上。突起12形成在晶片的每个光束11的中心。突起12涂覆有作为接触器的金属膜13，并且形成用于连接到晶片的另一侧的电极。用于连接接触器和电极的布线14将涂覆在突起12上的金属膜13从梁11的一侧延伸到梁的另一侧，其中布线延伸以连接承包件和电极，因此布线不会在要检查的表面上延伸，并且防止短路。此外，梁11的双支撑梁结构提供足够的强度。

10. 发明专利

JP2003004658A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003004658A
公开(公告)日：2003-01-08
申请号：JP2001186317
申请日：2001-06-20
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所
发明人： SAIKAI HIDEHIKO
IPC分类号： G01B11/24 , G01N21/956 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To detect the defect of a TCP product by a visual inspection irrespective of a material for a sealing resin.
SOLUTION: In an inspection part 9 in a visual inspection apparatus, reflected light obtained by applying light to the TCP product 2 is changed into an image, and a processed value is compared with a reference value. As a result, a void in the sealing resin, the exposure of a lead and the exposure of a chip are detected.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过目视检查来检测TCP产品的缺陷，而与密封树脂的材料无关。解决方案：在目视检查装置的检查部9中，通过向TCP产品2施加光而获得的反射光变为图像，将处理值与基准值进行比较。结果，检测到密封树脂中的空隙，引线的暴露和芯片的暴露。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式