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1. 发明专利

JP2003017652A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2003017652A
公开(公告)日：2003-01-17
申请号：JP2001195803
申请日：2001-06-28
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , Hitachi Ulsi Systems Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KANEDA TAKESHI , ONO HIROSHI , NISHIDA TAKAFUMI , ARITA JUNICHI , SHIBAMOTO MASAKUNI , SUZUKI KAZUNARI , MIYAZAKI CHUICHI , ARAO OSAMU
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2224/97 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device realizing high reliability with simple constitution.
SOLUTION: A second semiconductor chip is mounted on with the underside thereof being joined to the main surface of a first semiconductor chip, the first semiconductor chip is mounted on with the underside thereof being joined to a substrate, a protecting film is formed on the whole surface of the first semiconductor chip except a bonding electrode part, and the first and the second semiconductor chips and wiring means of the substrate are connected by wire bonding.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种以简单结构实现高可靠性的半导体器件。解决方案：第二半导体芯片安装在其下侧，与第一半导体芯片的主表面接合，第一半导体芯片安装在其下侧与基板相连，保护膜整体上形成除了接合电极部分之外的第一半导体芯片的表面以及基板的第一和第二半导体芯片和布线装置通过引线接合连接。

2. 发明专利

JP2000077435A Semiconductor device and manufacture thereof 审中-公开
标题翻译：半导体器件及其制造
公开(公告)号：JP2000077435A
公开(公告)日：2000-03-14
申请号：JP24540698
申请日：1998-08-31
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MIYAKI YOSHINORI , SUZUKI KAZUNARI , OMODA DAISUKE
IPC分类号： H01L21/52 , H01L21/56 , H01L23/04 , H01L23/495 , H01L23/50
CPC分类号： H01L24/32 , H01L21/565 , H01L23/49503 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/83855 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/15747 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To enable semiconductor devices to be improved in yield in a semiconductor device assembly process by a method, wherein a semiconductor chip that is provided with electrodes on its main surfaces is fixed and bonded to support leads through the intermediary of an adhesive tape.
SOLUTION: Electrodes 11 are formed on the circuit forming surface 10X of a semiconductor chip 10 along its sides, inner leads 2A of leads 2 are electrically connected to the electrodes 11 through the intermediary of conductive wires 12, and the outer leads 2B of the leads 2 are each formed like a gull wing. Furthermore the semiconductor chip 10 is fixed and bonded to the leads 3B of support leads through the intermediary of an adhesive tape 8. That is, the adhesive tape 8 is continuously parted on the lead 3B of the support lead 3 in the longer direction of the support lead 3 as it is partially led outside of the semiconductor chip 10.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：通过一种方法使半导体器件组装过程中的半导体器件的产量提高，其中在其主表面上设置有电极的半导体芯片被固定并结合以通过粘合剂的中间来支撑引线胶带。解决方案：电极11沿着半导体芯片10的侧面形成在半导体芯片10的电路形成表面10X上，引线2的内部引线2A通过导线12和电极12的引线电连接到电极11， 2分别形成为鸥翼。此外，半导体芯片10通过粘合带8固定并结合到支撑引线的引线3B上。也就是说，粘合带8沿着支撑引线3的引导件3B沿着长度方向连续分开支撑引线3，因为它被部分地引导到半导体芯片10的外部。

3. 发明专利

JP2003007913A Method of manufacturing semiconductor device and semiconductor module 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：JP2003007913A
公开(公告)日：2003-01-10
申请号：JP2001193042
申请日：2001-06-26
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SHIBAMOTO MASAKUNI , SUZUKI KAZUNARI , MIYAKI YOSHINORI
IPC分类号： H01L23/12
CPC分类号： H01L24/97
摘要： PROBLEM TO BE SOLVED: To prevent degradation in the reliability of a semiconductor device or a semiconductor module due to the warpage of a wiring board (carrier material), and to reduce an assembly failure due to the warpage of the wiring board (carrier material). SOLUTION: The wiring board (carrier material) is bonded onto a supporting plane by bonding whose adhesive power is strong and whose peeling is easy. A plurality of semiconductor elements or semiconductor modules (chips) are loaded in prescribed positions on the upper face of the wiring board. The outer terminal (pad) of the semiconductor element and a wiring terminal are electrically connected by an electric connection material. The semiconductor element, the electric connection material and a connection part where the outer terminal and the wiring terminal are electrically connected are mold-sealed by resin and the like. The wiring board is peeled from the supporting plane and a terminal for outer device connection is formed in the outer terminal of the semiconductor module at the back of the peeled wiring board. The device including the respective semiconductor elements or the semiconductor module elements is separated.
摘要翻译：要解决的问题：为了防止由于布线板（载体材料）的翘曲导致的半导体器件或半导体模块的可靠性的劣化，并且为了减少由于布线板（载体材料）的翘曲引起的组装故障，。解决方案：接线板（载体材料）通过粘合力粘合在支撑平面上，粘合力强，剥离容易。多个半导体元件或半导体模块（芯片）被装载在布线板的上表面上的规定位置。半导体元件的外部端子（焊盘）和布线端子通过电连接材料电连接。半导体元件，电连接材料和外部端子和布线端子电连接的连接部分通过树脂等进行模制密封。接线板从支撑面剥离，并且在剥离的布线板的背面的半导体模块的外部端子中形成用于外部设备连接的端子。包括各个半导体元件或半导体模块元件的器件被分离。

4. 发明专利

JP2004349730A Resin sealed semiconductor device and its manufacturing process 审中-公开
标题翻译：树脂密封半导体器件及其制造工艺
公开(公告)号：JP2004349730A
公开(公告)日：2004-12-09
申请号：JP2004264288
申请日：2004-09-10
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TANAKA HIROAKI , HAGIWARA YASUHISA , SUZUKI KAZUNARI , NISHIDA TAKAFUMI
IPC分类号： H01L23/50
CPC分类号： H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/92247 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of enhancing the electrical reliability of a semiconductor device having a heat spreader, and a technology capable of enhancing the thermal reliability of a semiconductor device having a heat spreader. SOLUTION: In the resin sealed semiconductor device, (1) a heat spreader 1 is provided and part of an insulating layer 2 is led out from the circumferential edge of the heat spreader 1, (2) a through hole 3 is formed in each insulating layer 2 and a semiconductor chip 4 is secured to the surface of the insulating layer 2 through an adhesive layer 5 to close the through hole 3, and (3) arithmetic mean surface roughness Ra of the rear surface facing the chip mounting surface of the heat spreader 1 is set at 0.45 or above. Consequently, the problem of a resin sealed semiconductor device having a heat spreader that electrical and thermal reliability lowers is eliminated. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供能够提高具有散热器的半导体装置的电可靠性的技术，以及能够提高具有散热器的半导体装置的热可靠性的技术。解决方案：在树脂密封半导体器件中，（1）设置散热器1，并且绝缘层2的一部分从散热器1的周缘引出，（2）形成通孔3 在每个绝缘层2中，并且半导体芯片4通过粘合剂层5固定到绝缘层2的表面以封闭通孔3，和（3）面向芯片安装表面的后表面的算术平均表面粗糙度Ra 的散热器1设定在0.45以上。因此，消除了具有电热可靠性降低的散热器的树脂密封半导体器件的问题。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004140398A Method of manufacturing resin-sealed semiconductor device 有权
公开(公告)号：JP2004140398A
公开(公告)日：2004-05-13
申请号：JP2003426015
申请日：2003-12-24
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： MIYAKI YOSHINORI , SUZUKI HIROMICHI , SUZUKI KAZUNARI , NISHIDA TAKAFUMI , ITO FUJIO , TSUBOSAKI KUNIHIRO , KAMEOKA AKIHIKO , NISHI KUNIHIKO
IPC分类号： H01L21/56
CPC分类号： H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/01015 , H01L2924/01047 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of enhancing the production yield of a resin-sealed semiconductor device. SOLUTION: The method of manufacturing a resin-sealed semiconductor device to be provided is to form a die pad such that the area of the main surface on which a semiconductor chip is mounted is smaller than the area of the semiconductor chip and to seal the semiconductor chip and the die pad into a resin-sealed body. The semiconductor chip and the die pad are arranged in a cavity of a metal mold such that the gap between the rear face of the die pad and the inner wall face, which faces the former, of the cavity is narrower than the gap between the main surface of the semiconductor chip and the inner wall face, which faces the former, of the cavity by the thickness of the die pad. Since the resin is injected from a center gate simultaneously into the upper and the lower sides of the cavity to form the resin-sealed body, there is no possibility that the semiconductor chip is pushed upward by the resin filled in the filling region in the rear side of the semiconductor chip. As a result, the failure that the semiconductor chip, bonding wires, and the like are exposed outside the resin-sealed body is prevented, and the yield of the resin-sealed semiconductor device can be enhanced. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2004056136A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004056136A
公开(公告)日：2004-02-19
申请号：JP2003205757
申请日：2003-08-04
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： MIYAKI YOSHINORI , SUZUKI KAZUNARI , OMODA DAISUKE
IPC分类号： H01L21/52 , H01L23/50
CPC分类号： H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To protect the drop of a yield in an assembly process of a semiconductor device. SOLUTION: The semiconductor device has a semiconductor chip either one of whose principal surfaces has a plurality of electrodes formed on it, a resin sealer that seals the semiconductor chip, a plurality of reeds that are electrically connected to the electrodes of the semiconductor device and extend over the inside and outside of the resin sealer, and a supporting reed that partially supports the other principal surface opposed to the principal surface of the semiconductor chip wherein the semiconductor chip is firmly fastened to the supporting reed with an adhesive tape. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2004172647A Semiconductor device 审中-公开
公开(公告)号：JP2004172647A
公开(公告)日：2004-06-17
申请号：JP2004069427
申请日：2004-03-11
申请人： Hitachi Ulsi Systems Co Ltd , Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKAHASHI NORIYUKI , SUZUKI MASAYUKI , TSUCHIYA KOJI , MATSUURA TAKAO , HASHIZUME TAKANORI , ICHITANI MASAHIRO , SUZUKI KAZUNARI , NISHIDA TAKAFUMI , IMURA KENICHI , MIWA TAKASHI
IPC分类号： H01L23/29 , H01L23/12 , H01L23/31
CPC分类号： H01L24/97 , H01L24/73 , H01L2224/32225 , H01L2224/45 , H01L2224/45015 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2224/85 , H01L2924/00 , H01L2924/00014 , H01L2924/20752
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device. SOLUTION: In a semiconductor device 1 which is configured to seal a semiconductor chip 8 mounted on the main plane of a package board 2 with sealing material 11, a conductor pattern 4 for wiring is arranged on the main plane and rear planes of the package board 2; and a dummy conductor pattern 4 is arranged on the area on which the wiring conductor pattern 4 is not arranged. By increasing the density of the conductor patterns 4 on the package board 2 in this manner, warpage or undulation or the like of the package board 2 due to the heat treatment in the production steps of the semiconductor device 1 may be reduced. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2004048024A Semiconductor integrated circuit device and its manufacturing method 有权
公开(公告)号：JP2004048024A
公开(公告)日：2004-02-12
申请号：JP2003207142
申请日：2003-08-11
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： KAJIWARA YUJIRO , SUZUKI KAZUNARI , TSUBOSAKI KUNIHIRO , SUZUKI HIROMICHI , MIYAKI YOSHINORI , NAITO TAKAHIRO , KAWAI SUEO
IPC分类号： H01L23/50 , H01L21/48 , H01L21/52 , H01L21/60 , H01L23/495
CPC分类号： H01L24/743 , H01L21/4842 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/02166 , H01L2224/29007 , H01L2224/2919 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/743 , H01L2224/82181 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/85181 , H01L2224/859 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, suitable for manufacturing a small quantity multi-kind large-scale integrated circuit package, and to provide a method for manufacturing the same. SOLUTION: In the semiconductor integrated circuit device including a semiconductor chip 2, having an integrated circuit and a plurality of bonding pads on one main surface, a die pad 3 partly connected to other main surface of an opposite side to the main surface of the chip 2, a plurality of leads 5 extended at its tip to a periphery of the chip 2, a plurality of bonding wires for connecting the plurality of the lads 5 to a plurality of bonding pads of the chip 2, and a sealer for resin-sealing the chip 2, the plurality of the leads 5, the pad 3 and the plurality of the bonding wires, a distance between the pad 3 and the tips of the plurality of the leads 5 is different, in response to the profile size of the placed chip 2. COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2004048022A Method for manufacturing semiconductor integrated circuit device 有权
公开(公告)号：JP2004048022A
公开(公告)日：2004-02-12
申请号：JP2003207140
申请日：2003-08-11
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： KAJIWARA YUJIRO , SUZUKI KAZUNARI , TSUBOSAKI KUNIHIRO , SUZUKI HIROMICHI , MIYAKI YOSHINORI , NAITO TAKAHIRO , KAWAI SUEO
IPC分类号： H01L23/50 , H01L21/48 , H01L21/52 , H01L21/60 , H01L23/495
CPC分类号： H01L24/743 , H01L21/4842 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/02166 , H01L2224/29007 , H01L2224/2919 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/743 , H01L2224/82181 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/85181 , H01L2224/859 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To improve the reflow crack resistance of a large-scale integrated circuit device. SOLUTION: A method for manufacturing the large-scale integrated circuit device includes a step of preparing a lead frame 1, having a plurality of inner leads disposed so as to surround a die pad 3 partly connected to the rear surface of a semiconductor chip 2 to be placed on the die pad 3 and the chip 2 placed on the pad 3, a step of coating a plurality of positions of the pad 3 of the prepared frame 1, a step of adhering the chip 2 having a plurality of electrodes on a surface with an adhesive 15 coating on the plurality of the positions to the pad 3 via the adhesive 15, a step of connecting the plurality of the electrodes of the chip 2 to the plurality of the inner leads, and a step of sealing the chip 2, the plurality of the inner leads and the pad 3 with a resin. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2005101669A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005101669A
公开(公告)日：2005-04-14
申请号：JP2005004077
申请日：2005-01-11
申请人： Hitachi Ulsi Systems Co Ltd , Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO FUJIO , TANAKA HIROAKI , SUZUKI HIROMICHI , TOIDA TOKUJI , KONNO TAKASHI , TSUBOSAKI KUNIHIRO , TANAKA SHIGEKI , SUZUKI KAZUNARI , KAMEOKA AKIHIKO
IPC分类号： H01L23/50
CPC分类号： H01L2224/05554 , H01L2224/32245 , H01L2224/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To stabilize the bonding of a narrow lead pitch and prevent the package crack of a semiconductor device provided with a heatsink. SOLUTION: In a semiconductor device provided with a heatsink, the lead width w and the lead plate thickness t of the tip end of an inner lead connected to a semiconductor chip is set to be w COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了稳定窄引线间距的接合，并防止设置有散热片的半导体器件的封装裂纹。解决方案：在具有散热器的半导体器件中，连接到半导体芯片的内引线的前端的引线宽度w和引线板厚度t设定为w

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