专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明专利

JPS6376199A ANALOG MEMORY CIRCUIT 失效
公开(公告)号：JPS6376199A
公开(公告)日：1988-04-06
申请号：JP21955686
申请日：1986-09-19
申请人： HITACHI LTD
发明人： IZAWA YUJI , MATSUI KAZUMASA , FURUHATA MAKOTO , MINAMIMURA EIJI
IPC分类号： G11C27/04
摘要： PURPOSE:To remove and decrease a harmful fixed pattern noise by providing address circuits respectively at the memory circuits of a parallel part, keeping constant concerning to the relative timing relation of the writing and reading of a signal and shifting the timing of an action at every sample concerning the section between memory circuits. CONSTITUTION:The (m) pieces of parallel part memory circuits 1-1-1-m and vertical shift registers 2-1-2-m are drive by control signals phi1SphimS, phi1CR-phimCR, phi1CW-phimCW and phi1W-phimW shifted at every clock sent from an input side horizontal shift register 5 and an output side horizontal shift register 6. Consequently, an input signal Vin written in the sequence into respective parallel part memory circuits 1-1-1-m at every clock at the input side is read as output signals V1-Vm in the same sequence as this. Further, these output signals are selected in the same sequence as that at the time of writing by analog switches 3-1-3-m, goes to an output signal Vout and the input/output of a continuous analog signal can be realized.

32. 发明专利

JPS62281192A ANALOG CONDENSOR MEMORY 失效
公开(公告)号：JPS62281192A
公开(公告)日：1987-12-07
申请号：JP12331686
申请日：1986-05-30
申请人： HITACHI LTD
发明人： IZAWA YUJI , MATSUI KAZUMASA , FURUHATA MAKOTO , MINAMIMURA EIJI
IPC分类号： G11C11/24 , G11C11/34
摘要： PURPOSE:To realize high speed and highly accurate operation by providing an electrostatic shield electrode to an input wire of an amplifier used for a parallel section and an input/output wire of the parallel section and a capacitor so as to reduce the inter-line coupling capacitance. CONSTITUTION:Lower electrodes 74, 75 of the capacitor are made of polysilicon on a conductive substrate 72 and a field oxide film 73 and parallel section input wires S11, S12, parallel section output wires So1, So2 and input wires SC2, SC3 are made of aluminum on the upper part of the capacitor forming film 76. Then an electrostatic shield electrode 78 is formed on it by aluminum vapor- deposition via an inter-layer insulation film 77. A sufficient effect is obtained for the electrostatic shield electrode 78 by connecting it to ground or power supply. Through the provision of the electrostatic shield electrode in this way, the coupling capacitance between the input/output wires is reduced remarkably and the fixed pattern noise and the gain reduction are reduced.

33. 发明专利

JPS61245567A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61245567A
公开(公告)日：1986-10-31
申请号：JP8637385
申请日：1985-04-24
申请人： HITACHI LTD
发明人： YAMAZAKI KOICHI , FURUHATA MAKOTO , WATANABE KAZUO
IPC分类号： H01L27/082 , G11C11/41 , G11C15/04 , H01L21/8226 , H01L21/8229 , H01L27/02 , H01L27/10 , H01L27/102 , H03K19/082
摘要： PURPOSE:To reduce an isolation region in a logic element, and to miniaturize a chip by mutually collecting and arranging I Ls, which are brought to the same phase and activated mutually, in three-state type I Ls to the same semiconductor island. CONSTITUTION:Five I Ls constituting each memory cell M are divided into three groups G1-G3 of L1 and L2, L3 and L4 and L5, collected and disposed to an epitaxial layer island 11 consisting of the same semiconductor, and insulated and isolated 13. A collector for the I L is represented by C, a base by B and an injector by INJ. The states of the three-state type I L (L1 and L2) of the group G1 are all displayed by word select signals +phi in the positive phase and controlled mutually by the same phase, the states of the three-state type I L (L5) of the G2 are displayed by word select signals -phi in the opposite phase and controlled mutually by the same phase among the memory cells, and reference potential regions are grounded at all times in I L (L3, L4) of the G3. According to the constitution, when the states of several three-state type I L are controlled at every island unit, the isolation regions 13 among I L can be reduced largely, and can also be omitted among the memory cells, thus miniaturizing the size of a chip, then easily manufacturing I L-RAM having large capacitance.

34. 发明专利

JPS61194697A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61194697A
公开(公告)日：1986-08-29
申请号：JP3434285
申请日：1985-02-25
申请人： HITACHI LTD
发明人： WATANABE KAZUO , FURUHATA MAKOTO , YAMAZAKI KOICHI
IPC分类号： G11C11/34 , G11C7/00
摘要： PURPOSE:To increase an operation speed, to simplify the constitution of a circuit, and to increase integration density and storage capacity by connecting only storage cells in a selected row to bit lines by tri-state gates. CONSTITUTION:When a word line W1 for writing is selected and driven, only tri-state gates S1 and S2 directed from bit lines B1 and B2 to the side of ILLs (L1 and L2) generate two high and low logical outputs, and remaining tri-state gates S3 and S4 enter an electrically neutral high-impedance state. Consequently, only storage cells M in the selected row are connected to the bit lines B1 and B2 and write data Din from a data input buffer 3 is written; and storage cells in other unselected rows are disconnected from the bit lines B1 and B2 completely. Further, when a word line W2 for reading is selected and driven, only tri- state gates S3 and S4 directed from the IIs (L1 and L2) to the bit lines B1 and B2 generate two high and low logical outputs.

35. 发明专利

JPS61183951A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61183951A
公开(公告)日：1986-08-16
申请号：JP2343685
申请日：1985-02-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKABE TAKAHIRO , NORISUE KATSUHIRO , HAYASHI MAKOTO , WATABE TOMOYUKI , MATSUMOTO KEIZO , FURUHATA MAKOTO , OGURA SADAO
IPC分类号： H01L27/082 , H01L21/8222 , H01L21/8226 , H01L21/8229 , H01L27/10 , H01L27/102
摘要： PURPOSE:To increase the degree of freedom in standardizing RAM construction of peripheral circuits by facilitating the electrical isolation of memory cells in action from memory cells in hold, by a method wherein the emitter of the coupling transistor of a RAM cell using the conventional I L is isolated from the ground terminal of the I L, and a coupling transistor is replaced with a forward NPN transistor. CONSTITUTION:NPN transistors Q3, Q4 connected to each other by crossing and PNP transistors Q1, Q2 acting as loads are constructed by mutual wiring by 2 gates of I Ls. Q1 plus Q4 and Q2 plus Q3 correspond to the I L gate each. Q5, Q6 are normal NPN transistors, i.e. reversely acting transistors in the forwardly acting NPN transistor. Therefore, Q5, Q6 act reversely to Q3, Q4. A word line W is the injector line of the I L, and a constant current source is connected to this line W during action.

36. 发明专利

JPS6175672A Signal processing circuit 失效
标题翻译：信号处理电路
公开(公告)号：JPS6175672A
公开(公告)日：1986-04-18
申请号：JP19670384
申请日：1984-09-21
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： YAMAMOTO MOROHISA , FURUHATA MAKOTO
IPC分类号： H04N5/04 , H04N5/06
摘要： PURPOSE: To decrease transfer of noise components to other electronic circuit by installing a signal transfer line between a control signal generating circuit to control on and off an electronic switch and the electronic switch in a semiconductor integrated circuit to remove the equalizing pulse.
CONSTITUTION: For setting, resetting and flip-flops FF
1 , FF
2 in the initial condition, a Q output is in a high level, an electronic switch SW is in the on condition and a Q
2 output of a counter 3 is in a high level. When a horizontal synchronizing signal V
1 of a high level is supplied to a terminal 1, FF
2 is reset, the Q output is changed to a low level and the counter 3 starts count. Next, when the horizontal synchronizing signal V
1 is changed to a low level, FF
1 is reset, the Q output is changed to the low level and a switch SW is turned off. When 50μscc passes from the condition. The Q
2 output of the counter 3 becomes a high level only for a constant time, the Q output of FF
2 also becomes a high level, the counter 3 is reset, simultaneously the Q output of FF
1 becomes a high level and the switch SW becomes an on condition. Consequentl,y, a horizontal synchronizing signal VH is obtained through a switch SW from a terminal 2.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在控制信号发生电路之间安装信号传输线以控制电子开关和电子开关的电子开关以及半导体集成电路中的电子开关以消除均衡脉冲，来减少噪声分量到其他电子电路的传输。构成：为了在初始状态下设置，复位和触发器FF1，FF2，Q输出处于高电平，电子开关SW处于导通状态，计数器3的Q2输出处于高电平。当将高电平的水平同步信号V1提供给端子1时，FF2被复位，Q输出变为低电平，并且计数器3开始计数。接下来，当水平同步信号V1变为低电平时，FF1被复位，Q输出变为低电平，开关SW断开。当50muscc从条件通过。计数器3的Q2输出仅在恒定时间内变为高电平，FF2的Q输出也变为高电平，计数器3复位，同时FF1的Q输出变为高电平，开关SW变为在条件。结果，y，通过来自端子2的开关SW获得水平同步信号VH。

37. 发明专利

JPS6126325A Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：JPS6126325A
公开(公告)日：1986-02-05
申请号：JP14684684
申请日：1984-07-17
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OKABE TAKAHIRO , HAYASHI MAKOTO , NORISUE KATSUHIRO , FURUHATA MAKOTO , WATABE TOMOYUKI , WASHIO YOSHITADA
IPC分类号： H03K19/091 , H03K19/177
摘要： PURPOSE: To decrease power consumption by dividing a logic circuit having lots of input line numbers into plural circuit blocks with a few number of input lines and using only a part while bringing them into the operating state.
CONSTITUTION: The 1st logic circuit DEC
ϕ inputs the 1st input group IW
1 , and is provided with j-set of output terminals D
1 ∼D
j , and outputs AND output through the combination of input signals. Only a part of optional logic circuits DEC
1 ∼ DEC
j is brought into the operating state by using a function of the circuit DEC
ϕ so as to provide a proper signal to the input line group IW
1 . Since only one among the j-set of logic circuits DEC
1 ∼DEC
j is operative, the power consumption is reduced remarkably in comparison with the conventional logic circuit.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过将具有大量输入行号的逻辑电路划分为具有少数输入线的多个电路块并且仅使部件同时使其进入工作状态来降低功耗。构成：第一逻辑电路DECphi输入第一输入组IW1，并提供j组输出端子D1-Dj，并通过输入信号的组合输出AND输出。只有部分可选逻辑电路DEC1- DECj通过使用电路DECphi的功能进入运行状态，以向输入线组IW1提供适当的信号。由于在j组的逻辑电路DEC1〜DECj中只有一个是可操作的，所以与传统的逻辑电路相比，功耗明显降低。

38. 发明专利

JPS6013532B2 失效
公开(公告)号：JPS6013532B2
公开(公告)日：1985-04-08
申请号：JP1501877
申请日：1977-02-16
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H04B1/04 , H04B1/40 , H04B1/54

39. 发明专利

JPS57194564A SIMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57194564A
公开(公告)日：1982-11-30
申请号：JP7921981
申请日：1981-05-27
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H01L27/082 , G05F3/26 , H01L21/331 , H01L21/8222 , H01L29/73
摘要： PURPOSE:To simplify and miniaturize the circuit by a method wherein the current mirror circuit comprises the common terminal provided with the multiple collectors in the base region where one collector and the base are shortcircuited as the input terminal and the other collectors as the output terminal. CONSTITUTION:An N type epitaxial layer 2 is formed on a P type substrate 1 as an emitter through the intermediary of the N embedded layer 4 and the inverse transistor provided with the multiple N type collectors 6 on the P type base 5 formed on said layer 2 is further formed while the current mirror circuit comprises the common terminal shortcircuiting one collector C2 and the base 5 as the input terminal and the other collector C1 as the output terminal grounding said emitter 2. Through these procedures, the circuit may be simplified and miniaturized.

40. 发明专利

JPS57173291A RECORDING AND REPRODUCING DEVICE FOR TV SIGNAL OF PAL SYSTEM 失效
公开(公告)号：JPS57173291A
公开(公告)日：1982-10-25
申请号：JP5856481
申请日：1981-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAGAWA HIMIO , KUDOU MITSURU , FURUHATA MAKOTO , YAMAMOTO MOROHISA
IPC分类号： H04N9/84 , H04N9/83
摘要： PURPOSE:To obtain an accurate fH/8 offset by generating a signal of (fSC+ 40fH+fH/8) by using a signal of (40fH+fH/8) and a signal of fSC during recoding and reproduction of a PAL system signal. CONSTITUTION:A chromaticity signal is inputted from a switch 3, a horizontal synchronizing signal from a terminal 13, and a head switch pulse from a terminal 27. A frequency dividing circuit 34 divides the frequency of the horizontal synchronizing signal by 321, and a VCO35 oscillates at 321fH. A frequency dividing circuit 36 divides the output frequency of the VCO35 by two to supply a signal of 160fH+fH/2 to a frequency dividing circuit 16, which outputs an accurate 40fH+fH/8 signal. A VXO22 compares the phase of a burst signal from a switch 21 with that of a PD23 to oscillate at fSC. Consequently, the output of the VXO22 and that of a four-phase shifting circuit 18 are multiplied mutually by a multiplying circuit 19 to obtain an accurate offset of fSC+40fH+fH/8 from a BPF20.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式