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    • 1. 发明专利
    • Memory structure
    • 内存结构
    • JP2007335076A
    • 2007-12-27
    • JP2007204671
    • 2007-08-06
    • Telefon Ab Lm Ericssonテレフォンアクティエボラゲット エルエム エリクソン
    • SOEDERQUIST INGEMAR
    • G06F12/06G11C27/04G06F12/04
    • G06F12/04
    • PROBLEM TO BE SOLVED: To provide a new memory structure for storing memory vectors.
      SOLUTION: Each of the storage positions (#1, Mi-#M, Mi) of the memory has a length adapted to the length of large vectors and is parallelly arranged extending from an input and/or output for information and deeper into the memory. In this way each vector is stored undivided in a sequential order with the beginning of the vector at the input and/or output of the memory (memory field F1 in memory plane Mi). Addressing is made to the input and/or output of the memory. There are means (1IB-MIB, 1UB-MUB) acting like shift registers for the inputting and outputting of information in undivided sequence to/from the storage positions in the memory.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供用于存储存储器向量的新的存储器结构。 解决方案:存储器的每个存储位置(#1,Mi-#M,Mi)具有适应于大向量长度的长度,并且平行地布置成从输入和/或输出延伸以用于信息和更深的 进入记忆。 以这种方式,每个向量在存储器(存储器平面Mi中的存储器字段F1)的输入和/或输出处以顺序的顺序存储在矢量的开始处。 对存储器的输入和/或输出进行寻址。 存在作为移位寄存器的装置(1IB-MIB,1UB-MUB),用于在存储器中的存储位置向/从存储位置输入和输出未分割序列的信息。 版权所有(C)2008,JPO&INPIT
    • 5. 发明专利
    • TRANSFER REGISTER
    • JP2001176289A
    • 2001-06-29
    • JP35502799
    • 1999-12-14
    • SONY CORP
    • KANEMATSU MIKIO
    • G11C27/04H01L21/339H01L29/762H04N5/335H04N5/341H04N5/372
    • PROBLEM TO BE SOLVED: To secure the appropriate operating electric charge amount of signal electric charge independently of variation of power voltage and amplitude variation of a transfer clock caused by an external input. SOLUTION: An internal driver 4 has power voltage 5 V voltage-divided by voltage-divider resistors R1, R2. Then the driver 4 outputs a transfer clock ϕLH of 0 V-5 V based on a transfer clock ϕLH' by an external input, and supplies it to an electrode 1n of the last stage. In this way, the transfer clock ϕLH is bypassed by an internal register, thus a transfer clock ϕ LH having an appropriate bias value 0 V-5 V is generated to prevent the operating electric charge amount from being reduced due to the reduction of clock amplitude. Also, even when power voltage VDD is varied, potential balance can be kept by varying a voltage-divided value in accordance with its variation, and the operating electric charge amount is prevented from being reduced due to the variation of power voltage VDD.