专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP4152531A1 ELECTRONIC DEVICES HAVING ELECTRO-OPTICAL PHASE-LOCKED LOOPS 审中-公开
公开(公告)号：EP4152531A1
公开(公告)日：2023-03-22
申请号：EP22180863.7
申请日：2022-06-24
申请人： Apple Inc.
发明人： BOOS, Zdravko , BISMUTO, Alfredo , GUNZELMANN, Bertram R.
IPC分类号： H01S5/0687 , H04B10/63 , H03L7/113 , H03L7/087
摘要： An electronic device may include wireless circuitry clocked using an electro-optical phase-locked loop (OPLL) having primary and secondary lasers. A frequency-locked loop (FLL) path and a phase-locked loop (PLL) path may couple an output of the secondary laser to its input. A photodiode may generate a photodiode signal based on the laser output. A digital-to-time converter (DTC) may generate a reference signal. The FLL path may coarsely tune the secondary laser based on the photodiode signal until the secondary laser is frequency locked. Then, the PLL path may finely tune the secondary laser based on the reference signal and the photodiode signal until the phase of the secondary laser is locked to the primary laser. The photodiode signal may be subsampled on the PLL path. This may allow the OPLL to generate optical local oscillator signals with minimal jitter and phase noise.

2. 发明公开

EP3931968A1 GENERATOR AND METHOD FOR GENERATING A CONTROLLED FREQUENCY 有权
公开(公告)号：EP3931968A1
公开(公告)日：2022-01-05
申请号：EP20707852.8
申请日：2020-02-24
申请人： Semiblocks B.V.
发明人： VAN ELZAKKER, Michiel , VAN DER VALK, Rob , VAN NIEUWBURG, Kees
IPC分类号： H03L7/23 , H03L1/02 , H03L7/16 , H03L7/087 , H03L7/099 , H03L7/113

3. 发明公开

EP3063873A1 BOUCLE A VERROUILLAGE DE PHASE DUALE ET PILOTEE 审中-公开
标题翻译： POWERED两相回路
公开(公告)号：EP3063873A1
公开(公告)日：2016-09-07
申请号：EP13789233.7
申请日：2013-10-31
申请人： Ecole Polytechnique Fédérale de Lausanne (EPFL)
发明人： TANNER, Steve , ZHAO, Yazhou , FARINE, Pierre-André
IPC分类号： H03L7/113 , H03L7/087
CPC分类号： H03L7/113 , H03L7/085 , H03L7/087
摘要： The invention relates to a phase lock loop (100) comprising: - a loop filter (140), - a voltage controlled oscillator (150), - a frequency divider (160), - a frequency lock detector (113), able to emit a frequency lock indication signal (LOCK), - a digital phase and frequency comparator (110), - a charge pump (111), and - an analogue phase comparator (120). The loop is essentially characterized in that it further comprises a switch (130) equipped with an output connected to the loop filter (140), and with two inputs, this switch being able to selectively connect the first input, originating from the analogue phase comparator, to its output in response to the lock indication signal; and its second input, originating from the digital phase and frequency comparator, to its output, in the absence of the lock indication signal.

4. 发明公开

EP2141813A1 Fully integrated frequency synthesis using PWLL 审中-公开
标题翻译： Voll integrierte频繁合成mithilfe von PWLL
公开(公告)号：EP2141813A1
公开(公告)日：2010-01-06
申请号：EP08104637.7
申请日：2008-07-04
申请人： Aksin, Devrim
发明人： Aksin, Devrim , Basyurt, Pinar Basak , Uyanik, Hayri Ugur , Ates, Erdogan Ozgur
IPC分类号： H03L7/097 , H03L7/113 , H03K7/08
CPC分类号： H03L7/085 , H03K7/08 , H03L7/093 , H03L7/0995
摘要： The present invention proposes a frequency synthesizer whose output frequency is digitally controlled by way of locking the same to a voltage ratio rather than the phase of a time reference. The pulse width locked loop consists of a Loop Filter, a voltage controlled oscillator and a frequency to pulse width converter according to the present invention. Proposed FPWC modulates the pulse width of a pulse train with another frequency source and thus converts frequency input to a DC voltage. A high-resolution digital to analog converter is used to generate the loop control voltage. The reference signal of the digital frequency to pulse width converter is obtained using a differential Colpitts oscillator.
摘要翻译：本发明提出一种频率合成器，其输出频率通过将其锁定到电压比而不是时间基准的相位被数字地控制。脉冲宽度锁定环路由根据本发明的环路滤波器，压控振荡器和频率对脉冲宽度转换器组成。建议的FPWC用另一个频率源调制脉冲串的脉冲宽度，从而将频率输入转换为直流电压。高分辨率数模转换器用于产生环路控制电压。使用差分Colpitts振荡器获得数字频率到脉冲宽度转换器的参考信号。

5. 发明公开

EP1724926A1 PHASE LOCK CIRCUIT AND INFORMATION REPRODUCTION DEVICE 审中-公开
标题翻译： PHASENREGELKREIS UND INFORMATIONSWIEDERGABEEINRICHTUNG
公开(公告)号：EP1724926A1
公开(公告)日：2006-11-22
申请号：EP05710704.7
申请日：2005-02-25
申请人： SONY CORPORATION
发明人： SENBA, Kimimasa, SONY CORPORATION
IPC分类号： H03L7/087 , H03L7/113 , G11B20/14 , H04L7/033
CPC分类号： H04L7/033 , H03L7/087 , H03L7/091 , H03L7/0995 , H03L7/10
摘要： A PLL circuit and an information reproduction apparatus able to reduce an influence of erroneous detection even when erroneous detection of a frequency comparator occurs and able to realize stable and high speed frequency lock-in, having a frequency comparator 25 fetching a zero cross signal ZC in synchronization with clocks CLKA to CLKC from a VCO 23 and observing from which phase to which phase an edge of the zero cross changed in synchronization with the clock CLKA and thereby detecting high/low of the frequency as frequency error and outputting an up signal UP or a down signal DOWN, an integration circuit 26 integrating the signal UP or DOWN, a comparator 27 receiving the integrated up signal UP or down signal DOWN, judging a direction of the frequency error, and outputting three signals of UPM, DOWNM, and NONM, and a gain adjustment circuit 28 determining whether or not the signal is to be output or determining a feedback gain from the pattern of a sequence of the signals UPM, DOWNM, and NONM, and outputting the same.
摘要翻译：一种PLL电路和信息再现装置，即使在发生频率比较器的错误检测时也能够减少错误检测的影响，并且能够实现稳定且高速的频率锁定，其中频率比较器25获取零交叉信号ZC 与来自VCO 23的时钟CLKA至CLKC同步，并且观察与时钟CLKA同步地从零交叉的边缘到哪个相位的哪个相位，从而检测频率的高/低作为频率误差并输出上行信号UP或下降信号DOWN，积分信号UP或DOWN的积分电路26，接收积分上行信号UP或DOWN信号DOWN的比较器27，判断频率误差的方向，并输出UPM，DOWNM和NONM的三个信号，以及增益调整电路28，确定信号是否要输出，或者根据信号UPM，DOW的序列的图案确定反馈增益 NM和NONM，并输出。

6. 发明授权

EP1229655B1 Phase locked loop apparatus 有权
标题翻译：具有一个锁相环装置
公开(公告)号：EP1229655B1
公开(公告)日：2006-06-14
申请号：EP02250528.3
申请日：2002-01-25
申请人： Marconi Mobile SpA
发明人： Pomona, Ignazio , Russo, Mario , Leonardi, Orazio
IPC分类号： H03L7/087 , H03L7/22 , H03L7/113 , H03L7/20
CPC分类号： H03L7/20 , H03L7/087 , H03L7/091 , H03L7/113

7. 发明公开

EP1513310A1 Procédé et dispositif de correction du décalage fréquentiel de la fréquence porteuse d'un signal modulé avec une modulation monoporteuse continue en quadrature. 审中-公开
标题翻译：信号和信号（信号）信号和信号信号（Einzelträgerquadraturmodulierten）信号
公开(公告)号：EP1513310A1
公开(公告)日：2005-03-09
申请号：EP04292080.1
申请日：2004-08-24
申请人： STMicroelectronics S.A.
发明人： Paille, Bruno
IPC分类号： H04L27/00 , H04L27/38 , H03L7/113
CPC分类号： H04L27/0014 , H03L7/113 , H04L27/3818 , H04L2027/0055 , H04L2027/0057 , H04L2027/0081
摘要： On effectue une première estimation dudit décalage avec un estimateur de fréquence EST de façon à obtenir une première valeur d'estimation puis on affine l'estimation dudit décalage fréquentiel et on corrige en conséquence la fréquence porteuse, avec une boucle à verrouillage de phase PLL initialisée avec ladite première valeur d'estimation et dont la plage fréquentielle d'accrochage est inférieure à la plage fréquentielle d'accrochage de l'estimateur de fréquence.
摘要翻译：该方法包括以获得估计值的方式以频率估计器（EST）估计接收信号的载波频率的频移。改变频移的估计值。通过由估计值启动的锁相环（PLL）校正载波频率。 PLL的频率锁定范围低于估计器的频率锁定范围。还包括用于处理频移的设备的独立权利要求。

8. 发明授权

EP1005166B1 Method for detecting frequency of digital phase locked loop 有权
标题翻译：一种用于在数字相位检测频率方法锁相环
公开(公告)号：EP1005166B1
公开(公告)日：2005-02-16
申请号：EP99309397.0
申请日：1999-11-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Park, Hyun-Soo, 119-312, Hanshin Apt. , Shim, Jae-Seong , Won, Yong-Kwang
IPC分类号： H03L7/113 , G01R23/02
CPC分类号： H03L7/091 , G01R23/10 , G11B20/1403 , H03L7/113

9. 发明公开

EP1374387A4 SYSTEM FOR CONTROLLING THE FREQUENCY OF AN OSCILLATOR 有权
标题翻译：系统ZUR STEUERUNG DER FREQUENZ EINES OSZILLATORS
公开(公告)号：EP1374387A4
公开(公告)日：2004-05-26
申请号：EP02721582
申请日：2002-03-25
申请人： SKYWORKS SOLUTIONS INC
发明人： DAMGAARD MORTEN , DOMINO WILLIAM J , MAGOON RAHUL , MOLNAR ALYOSHA C , ZACHAN JEFF
IPC分类号： H03B1/00 , H03L5/00 , H03L7/087 , H03L7/099 , H03L7/113 , H03L7/187 , H04B1/40
CPC分类号： H03L7/099 , H03B2201/025 , H03B2201/0291 , H03J2200/10 , H03L5/00 , H03L7/087 , H03L7/113
摘要： Systems for controlling the frequency of the output signal of a controllable oscillator (202) in a frequency synthesizer (200) are provided. One such system comprises a controllable oscillator (202) and a frequency control circuit (208). The controllable oscillator (202) is configured to generate an output signal that has a predefined frequency. The controllable oscillator (202) is also configured with a plurality of operational states that are controlled by the frequency control circuit (208). Each operational state of the controllable oscillator (202) defines a distinct frequency for the output signal of the controllable oscillator (202). The frequency control circuit (208) receives the output signal of the controllable oscillator (202) and determines the distinct frequency for the output signal that best approximates the predefined frequency. The frequency control circuit (208) may also provide a control signal to the controllable oscillator (202) that is configured to change the controllable oscillator (202) to the operational state corresponding to the distinct frequency that best approximates the predefined frequency.
摘要翻译：提供了用于控制频率合成器中可控振荡器的输出信号的频率的系统。一个这样的系统包括可控振荡器和频率控制电路。可控振荡器被配置为产生具有预定频率的输出信号。可控振荡器还配置有由频率控制电路控制的多个操作状态。可控振荡器的每个操作状态为可控振荡器的输出信号定义了不同的频率。频率控制电路接收可控振荡器的输出信号，并确定最接近预定频率的输出信号的不同频率。频率控制电路还可以向可控振荡器提供控制信号，该控制信号被配置为将可控振荡器改变为对应于最接近于预定频率的不同频率的操作状态。

10. 发明授权

EP0907252B1 Phase-locked loop with improved trade-off between lock-up time and power dissipation 有权
标题翻译：具有之间的改进的锁定时间和功耗比PLL
公开(公告)号：EP0907252B1
公开(公告)日：2003-11-26
申请号：EP98118420.3
申请日：1998-09-29
申请人： Sanyo Electric Co., Ltd. , Tottori Sanyo Electric Co., Ltd.
发明人： Sumi, Yasuaki Tottori Sanyo Electric Co., Ltd.
IPC分类号： H03L7/00 , H03L7/113 , H03L7/089 , H03L7/18
CPC分类号： H03L7/0891 , H03K23/665 , H03K23/68 , H03L7/087 , H03L7/113 , H03L7/18 , H03L7/181 , H03L7/191 , H03L7/1974 , H03L7/199

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式