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1. 发明授权

EP1671422B1 PHASE-LOCKED LOOP BANDWIDTH CALIBRATION CIRCUIT AND METHOD THEREOF 有权转让
标题翻译：锁相环带宽校准电路及其方法
公开(公告)号：EP1671422B1
公开(公告)日：2017-04-12
申请号：EP04793967.3
申请日：2004-10-01
申请人： MediaTek Inc.
发明人： BALBONI, Edmund, J. , PALMER, Wyn, T. , STRANGE, Jonathan, R.
IPC分类号： H03L7/093
CPC分类号： H03L7/1976 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03J3/00 , H03L7/0805 , H03L7/0893 , H03L7/0898 , H03L7/093 , H04L2027/0081

2. 发明公开

EP1931098A2 Setting the gain of a loop filter used for carrier synchronization in a receiver according to the type of quadrature modulation received 审中-公开
标题翻译：设置取决于环路滤波器的增益为载波同步的接收的正交调制类型在接收器中
公开(公告)号：EP1931098A2
公开(公告)日：2008-06-11
申请号：EP07122127.9
申请日：2007-12-03
申请人： Sony Corporation
发明人： Iida, Jasuhiro , Funamoto, Kazuhisa
IPC分类号： H04L27/38
CPC分类号： H04L27/38 , H04L27/0014 , H04L2027/003 , H04L2027/0055 , H04L2027/0069 , H04L2027/0081 , H04L2027/0095
摘要： A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes:
a demodulation section (11) that demodulates the modulation signal into a demodulation signal including an Icomponent and a Qcomponent;
a numerically controlled oscillation section (37) that generates a signal of predetermined phase;
a phase error detection section (32) that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section (37);
a phase rotation section (33) that rotates the phase of the symbol of the demodulation signal in accordance with the phase error;
a loop filter (36) that filters the phase error, and controls the numerically controlled oscillation section; and
a gain control section (38) that controls a gain of the loop filter (36) based on a modulation technique of the modulation signal.
摘要翻译：一种接收装置，确实接收调制信号是载波的数字调制的结果，游离缺失盘。该装置包括：解调部（11）做解调调制信号转换成解调信号包含在IComponent的和Qcomponent; 数控振荡部分（37），其生成预定相位的信号; 一个相位误差检测部分（32）没有检测解调信号的码元的相位和由数控振荡部分（37）产生的信号的预定相位之间的相位误差; 相位旋转部（33）做旋转与所述相位误差雅舞蹈的解调信号的码元的相位; （36）做了环路滤波器滤波所述相位误差，并控制数字控制振荡部; 以及增益控制部（38）做了控制基于调制信号的调制技术的环路滤波器（36）的增益。

3. 发明公开

EP1047235A4 CARRIER PHASE ESTIMATOR DEVICE AND DEMODULATOR 审中-公开
标题翻译： TRÄGERPHASENSCHÄTZERSOWIE DEMODULATOR
公开(公告)号：EP1047235A4
公开(公告)日：2006-08-30
申请号：EP99922526
申请日：1999-05-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： FUJIMURA A , KOJIMA T
IPC分类号： H04L27/00 , H04L27/227 , H04L27/22
CPC分类号： H04L27/227 , H04L2027/0048 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081
摘要： A demodulator comprises nonlinear processing means (20) for removing the modulated components from received baseband signals to obtain unmodulated complex data; first moving average means (25a) for determining the moving average of unmodulated complex data; means (24) for determining the carrier phase from the vector angle represented by the moving average; and means (5) for determining filter bandwidth to control the bandwidth of the first moving average means (25a) by using the data of past r symbols in unmodulated complex data.
摘要翻译：该装置具有提取调制分量的非线性处理器，具有移动平均确定机制，载波相位确定机制和滤波器带宽确定以调节移动平均机制的带宽：解调器包括非线性处理器（20），用于从已接收到的调制分量中去除调制分量基带信号以获得未调制的复数数据。第一移动平均机构（25a）确定未调制的复数数据的移动平均值。进一步的机构（24）从由移动平均线表示的向量角度确定载波相位。滤波器带宽确定单元（5）通过使用未调制的复数数据中的过去r个符号的数据来控制第一移动平均装置的带宽。

4. 发明公开

EP1627467A1 METHOD AND ARRANGEMENT FOR AUTOMATIC FREQUENCY CONTROL IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：方法和设备的自动频率控制通信系统中的
公开(公告)号：EP1627467A1
公开(公告)日：2006-02-22
申请号：EP04733378.6
申请日：2004-05-17
申请人： IPWireless, Inc.
发明人： HOWARD, Paul
IPC分类号： H03J7/02 , H04L27/00 , H04L7/02
CPC分类号： H04L27/2272 , H03J7/02 , H04L2027/0081
摘要： An arrangement (900), method and unit for AFC in a communication system (100) having: a frequency estimator (980) producing a decision-directed frequency estimate from a received signal; and an AFC loop receiving the decision-directed frequency estimate and performing therewith frequency control. The AFC process may use a CRC-decision directed frequency estimate as the final stage in a multi-stage AFC process (preceded by SCH- and midamble-derived frequency estimate stages), such that a verified received data sequence is used to re-construct a local copy of the ideal received data symbols expected at the output of a detector. This local copy is then correlated with the actual detector output and the results used to estimate the frequency error present on the received signal. The AFC process is inherent suited for discontinuous receive (DRX) applications. This provides the advantage of allowing required frequency correction accuracy to have minimal impact on the error rate of the received data in various channel configurations.

5. 发明公开

EP1543631A1 VARIABLE-LENGTH CORRELATOR FOR SPREAD-SPECTRUM COMMUNICATIONS 审中-公开
标题翻译： CORRELATOR可变长度扩频
公开(公告)号：EP1543631A1
公开(公告)日：2005-06-22
申请号：EP03759304.3
申请日：2003-09-18
申请人： Thomson Licensing S.A.
发明人： LITWIN, JR., Louis, Robert
IPC分类号： H04B1/69 , H04L25/49 , H04L27/06 , H04L7/00 , H03D3/18 , H03D3/24
CPC分类号： H04B1/7075 , H04B1/7087 , H04B1/709 , H04L2027/003 , H04L2027/0081
摘要： An apparatus (400) and method (500) for providing variable-length correlation for spread-spectrum communications includes a derotator (412), a variable-length correlator (414) in signal communicationwith the derotator, a phase detector (416) in signal communication with the variable-length correlator, a lock detector (418) in signal communication with the phase detector, and a controller (420) in signal communication with the lock detector for controlling the length of the variable-length correlator; where the corresponding method to track out large frequency offsets in spread-spectrum communications includes receiving signal chips, correlating the received signal chips, computing a loop error in accordance with the correlation, setting a new lock status in accordance with the computed loop error and a previous lock status, and setting a new correlator length in accordance with the new lock status and a previous correlator length.

6. 发明公开

EP1202512A3 Frequency synchroniser which uses both analogue and digital control signals 有权
标题翻译：频率计算器，频谱分析仪
公开(公告)号：EP1202512A3
公开(公告)日：2004-02-11
申请号：EP01309108.7
申请日：2001-10-26
申请人： Nokia Corporation
发明人： Paatelma, Risto , Kuronen, Juha , Berg, Heikki
IPC分类号： H04L27/00
CPC分类号： H04L27/22 , H04L2027/0028 , H04L2027/0055 , H04L2027/0081
摘要： A frequency synchroniser is proposed, particularly for use in a mobile wireless receiver. Coarse synchronisation is controlled by an analogue signal, while fine synchronisation is controlled by a digital signal.
摘要翻译：提出了一种频率同步器，特别是用于移动无线接收机。粗同步由模拟信号控制，而精细同步由数字信号控制。

7. 发明公开

EP0874499A3 Analog-to-digital converter for digital receiver 失效
标题翻译： A / D WandlerfürdigitalenEmpfänger
公开(公告)号：EP0874499A3
公开(公告)日：2001-02-07
申请号：EP98202124.8
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H03K5/24 , H04L25/06
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An analog-to-digital converter apparatus, comprising a comparator having first and second units, each of said units comprising : a capacitor connected to a first node and a second node ; a first switch means for connecting said first node to a selected one of an input voltage and a reference voltage ; an inverter having an input connected to said second node, and an output; and a second switch means for connecting said output of said inverter to said second node of an other of said units.
摘要翻译：提供了一种利用多级残留边带传输的综合数字通信系统。通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。

8. 发明公开

EP0874491A2 Signal processing apparatus and method 失效
标题翻译：一种信号处理装置和方法
公开(公告)号：EP0874491A2
公开(公告)日：1998-10-28
申请号：EP98202126.3
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, Williams P. , Barnes, Mark Michael
IPC分类号： H04L1/00 , H03M13/22
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： A deinterleaving circuit for processing of a signal comprising blocks of interleaved data packets represented therein, comprising :

a random access memory for memorizing a data stream of said blocks of interleaved packets, wherein a capacity of said memory does not exceed any of said blocks ;
a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by an addressing interval ;
a second circuit for successively reading and writing data out of and into said random access memory respectively at a reading address and a writing address of said random access memory, said reading address and said writing address being determined by said address signal, wherein said address signal is constant during an operation comprising reading and writing data at said address ; and
a third circuit responsive to a signal ACCEPT_BLOCK for periodically increasing said addressing interval by a value equal to an interleaving depth of said interleaved packets wherein said signal ACCEPT_BLOCK is asserted after completion of an operation comprising a complete deinterleaving of one of said blocks of data.

9. 发明公开

EP0748124A2 Signal processing apparatus and method 失效
标题翻译： Signalverarbeitungsgerätund Verfahren
公开(公告)号：EP0748124A2
公开(公告)日：1996-12-11
申请号：EP96301869.2
申请日：1996-03-19
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony P.J. , Macfarlane, Charles D. , Gammack, Richard J. , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H04N7/52 , H04N7/60 , H04Q11/02
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.
摘要翻译：提供了一种利用多级残留边带传输的综合数字通信系统。通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。

10. 发明公开

EP0527249A1 Carrier recovery apparatus for digital satellite communication system 失效
标题翻译： Trägerrückgewinnungseinrichtungfürdigitale Satellitennachrichtensysteme。
公开(公告)号：EP0527249A1
公开(公告)日：1993-02-17
申请号：EP91113383.3
申请日：1991-08-09
申请人： NEC CORPORATION
发明人： Tsuda, Hiroki , Otani, Susumu
IPC分类号： H04L27/22
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0081
摘要： A carrier recovery apparatus, for burst mode reception, is described. The DPLL has two modes of operations, an acquisition mode used during the carrier recovery part of the burst, and a steady state mode used during the rest of the burst, including data reception.
The carrier recovery section of the burst is divided into a number of frames, and each frame into a number of sub - periods. During each sub - period, the DPLL operates with a particular bandwith, and the cycle of bandwidths is repeated in subsequent frames. At the start of each sub - period, the setting of the VCO (5) is restored to the setting at the end of the corresponding sub - period of the previous frame.
The power of the baseband signal is detected (7, 8, 9) for each sub - period of each frame, and this is used to determine the bandwidth which gives the best results.
At the end of the carrier recovery period, the DPLL switches to the steady state mode, and uses the bandwidth which gave the best results during the acquisition period.
摘要翻译：描述了用于突发模式接收的载波恢复装置。 DPLL具有两种操作模式，在脉冲串的载波恢复部分期间使用的采集模式以及在脉冲串的其余部分期间使用的稳态模式，包括数据接收。突发的载波恢复部分被划分成多个帧，每个帧分成多个子周期。在每个子周期期间，DPLL以特定的带宽操作，并且在随后的帧中重复带宽的周期。在每个子周期的开始，VCO（5）的设置恢复到在前一帧的相应子周期结束时的设置。对于每帧的每个子周期，检测基带信号的功率（7,8,9），这用于确定给出最佳结果的带宽。在载波恢复周期结束时，DPLL切换到稳态模式，并使用在采集周期中获得最佳结果的带宽。

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