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1. 发明公开

EP4395179A1 ELECTRONIC DEVICE, OPERATING METHOD THEREOF, AND ELECTRONIC SYSTEM 审中-公开
公开(公告)号：EP4395179A1
公开(公告)日：2024-07-03
申请号：EP23212178.0
申请日：2023-11-27
申请人： Samsung Electronics Co., Ltd.
发明人： CHOI, Youngho , LIM, Donghyuk , KWON, Kibaek
IPC分类号： H03L7/087 , H03L7/091 , H03L7/093 , H04L7/033
CPC分类号： H03L7/0807 , H04L7/0331 , H03L2207/0620130101 , H03L7/087 , H03L7/093 , H03L2207/5020130101 , H03L7/091
摘要： An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

2. 发明授权

EP3291447B1 DIGITAL PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME 有权
公开(公告)号：EP3291447B1
公开(公告)日：2018-12-05
申请号：EP16186301.4
申请日：2016-08-30
申请人： Stichting IMEC Nederland
发明人： VAN DEN HEUVEL, Johannes Henricus Cornelus , LIU, Yao-Hong
IPC分类号： H03L7/085
CPC分类号： H03L7/087 , G04F10/005 , H03L7/085 , H03L7/091 , H03L7/1976 , H03L2207/50
摘要： The present disclosure relates to a Digital Phase Locked Loop, DPLL, (1) for phase locking an output signal (2) to a reference clock signal (3). The DPLL (1) comprises a phase detector (5) for detecting a phase error of a feedback signal (6) with respect to the reference clock signal (3). The DPLL (1) comprises a digitally controlled oscillator (7) for generating the output signal (2) based at least on a frequency control word (8) and at least one control signal (11, 13) representative of the phase error. The phase detector (5) comprises an integer circuit (9) for generating a first control signal (11) representative of an integer phase error. The phase detector (5) comprises a fractional circuit (12) comprising a Time-to-Digital Converter, TDC, (14) for processing the feedback signal (6) and a delayed reference clock signal (4). The fractional circuit (12) is provided for generating from the TDC output (15) a second control signal (13) representative of a fractional phase error. The DPLL (1) comprises an unwrapping unit (17) for unwrapping the TDC output (15).

3. 发明授权

EP1816741B1 Phase detector 有权
公开(公告)号：EP1816741B1
公开(公告)日：2018-10-03
申请号：EP07108304.2
申请日：2001-07-02
申请人： Texas Instruments Incorporated
发明人： Staszewski, Robert B. , Leipold, Dirk
IPC分类号： H03D13/00 , H03L7/091 , H03L7/085
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/50
摘要： A digital fractional phase detector (200) is provided to realize a frequency synthesizer architecture (100) that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO (104) and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector (200) is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock (110) and a reference clock by using a time-to-digital converter (201) to express the time difference as a digital word for use by the frequency synthesizer.

4. 发明授权

EP3158677B1 AN APPARATUS FOR SYNCHRONIZING A SAMPLING SIGNAL ON A COMMUNICATION SIGNAL 有权
公开(公告)号：EP3158677B1
公开(公告)日：2018-09-12
申请号：EP14747327.6
申请日：2014-07-22
申请人： Huawei Technologies Co., Ltd.
发明人： STOJANOVIC, Nebojsa
IPC分类号： H04L7/00 , G11B20/10 , H03L7/087 , H04B10/61
CPC分类号： H04L7/0008 , H03J7/00 , H03L7/0807 , H03L7/091 , H04B10/61 , H04L7/0029 , H04L7/0335
摘要： The invention relates to an apparatus (100) for synchronizing a sampling signal on a communication signal, the communication signal comprising communication symbols, the sampling signal indicating sampling time instants of the communication signal, the apparatus (100) comprising a sampler (101) being configured to sample the communication signal at the sampling time instants indicated by the sampling signal to obtain a sampled communication signal, a filter (103) being configured to filter the sampled communication signal using a first filtering transfer function to obtain a first filtered sampled communication signal, and to filter the sampled communication signal using a second filtering transfer function to obtain a second filtered sampled communication signal, a phase detector (105) being configured to determine a first phase detection signal upon the basis of the first filtered sampled communication signal, and to determine a second phase detection signal upon the basis of the second filtered sampled communication signal, the first phase detection signal indicating a position of a sampling time instant within a communication symbol of the first filtered sampled communication signal, the second phase detection signal indicating a position of a sampling time instant within a communication symbol of the second filtered sampled communication signal, a determiner (107) being configured to determine a first synchronicity measure upon the basis of the first phase detection signal, and to determine a second synchronicity measure upon the basis of the second phase detection signal, the first synchronicity measure and the second synchronicity measure indicating a synchronicity between the sampling signal and the communication signal, and a selector (109) being configured to select the first filtering transfer function or the second filtering transfer function of the filter (103) for filtering the sampled communication signal upon the basis of the first synchronicity measure and the second synchronicity measure for synchronizing the sampling signal on the communication signal.

5. 发明公开

EP3346610A1 PROZESSOR ZUM BESTIMMEN EINER PHASE EINES EMPFANGSSIGNALS BASIEREND AUF EINER EMPFANGSSEQUENZ ABGETASTETER WERTE 有权转让
公开(公告)号：EP3346610A1
公开(公告)日：2018-07-11
申请号：EP18151321.9
申请日：2015-10-14
申请人： SoNovum AG
发明人： Wrobel, Miroslaw , Kolany, Adam
IPC分类号： H03L7/091 , G01R19/25
CPC分类号： H03L7/091 , G01R19/25 , G01R19/2506 , H04M1/24 , H04M3/2209 , H04M3/30
摘要： Die Erfindung betrifft einen Prozessor (400, 500) zum Bestimmen einer Phase eines Empfangssignals, mit: einem Eingangsregister (401), das ausgelegt ist, einen Empfangswert eines mit bekannter Abtastfrequenz f S abgetasteten Empfangssignals (Y) zu speichern, wobei das Empfangssignal (Y) eine Reaktion auf ein Sendesignal mit einer bekannten Sendefrequenz f W darstellt; einem ersten Koeffizientenregister (403) und zweiten Koeffizientenregister (405), die ausgelegt sind, einen ersten (S) und einen zweiten (C) Fourier-Koeffizienten zu speichern, wobei der erste Fourier-Koeffizient (S) eine lineare Beziehung zwischen dem Empfangssignal (Y) und einem Phasenrealteil des Empfangssignals (Y) angibt und der zweite Fourier-Koeffizient (C) eine lineare Beziehung zwischen dem Empfangssignal (Y) und einem Phasenimaginärteil des Empfangssignals (Y) angibt; einem ersten Ausgangsregister (407) und einem zweiten Ausgangsregister (409), die ausgelegt sind, einen Phasenrealteil (U) und einen Phasenimaginärteil (V) des Empfangssignals (Y) bereitzustellen; und einer Recheneinheit (411), die ausgelegt ist, den Phasenrealteil (U) des Empfangssignals (Y) basierend auf einem gemittelten Produkt des Empfangswertes mit dem Inhalt (S) des ersten Koeffizientenregisters (403) zu bestimmen und den Phasenimaginärteil (V) des Empfangssignals (Y) basierend auf einem gemittelten Produkt des Empfangswertes mit dem Inhalt (C) des zweiten Koeffizientenregisters (405) zu bestimmen.

6. 发明授权

EP3041162B1 MONITORING AND CONTROL OF REFERENCE CLOCKS TO REDUCE BIT ERROR RATIO 有权转让
标题翻译：监视和控制参考时钟以减少位错误率
公开(公告)号：EP3041162B1
公开(公告)日：2018-05-09
申请号：EP15202484.0
申请日：2015-12-23
申请人： Ciena Corporation
发明人： BARROW, Shawn
IPC分类号： H04L7/033 , H03L7/091 , H03M1/06
CPC分类号： H04L1/0036 , H03L7/00 , H03L7/091 , H03M1/0639 , H04J3/0685 , H04L1/00 , H04L1/0046 , H04L1/20 , H04L7/0054 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L7/048
摘要： A method for reducing a frequency error, including: applying (205) a plurality of dither values to a local reference clock over a first time interval; sampling (210), during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, where the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; tracking (215) a plurality of errors from sampling the first plurality of data values; and adjusting (230), based on the plurality of errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

7. 发明授权

EP3119000B1 ALL DIGITAL PHASE LOCKED LOOP 有权
标题翻译：全数字锁相环
公开(公告)号：EP3119000B1
公开(公告)日：2018-03-28
申请号：EP15177206.8
申请日：2015-07-17
申请人： Stichting IMEC Nederland
发明人： van den Heuvel, Johannes Henricus Cornelus
IPC分类号： H03L7/085
CPC分类号： H03L7/0814 , H03L7/085 , H03L7/091 , H03L7/093 , H03L2207/50
摘要： The present invention relates to an all-digital Phase-Locked Loop comprising - a reference phase generator (PHR) arranged for receiving a digital signal and for splitting the digital signal into an integer part (PHR_I) and a fractional part (PHR_F), - an estimator block (20) arranged for estimating a control signal, - a digital-to-time converter (30) arranged for receiving the estimated control signal and a reference clock signal (FREF) and arranged for deriving a delayed reference clock signal () using the reference clock signal and the estimated control signal, - a time-to-digital converter (40) arranged for receiving the delayed reference clock signal and a desired clock signal phase () and for deriving a fractional phase error, characterised in that the estimator block is arranged for receiving the fractional phase error and for determining the estimated control signal by * correlating the fractional phase error with a version () of said fractional part having zero mean, yielding a correlated signal (), * multiplying the correlated signal with its absolute value, * integrating the outcome () of said multiplying to so obtain the estimated control signal.

8. 发明公开

EP3269040A1 PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
标题翻译：锁相环（PLL）结构
公开(公告)号：EP3269040A1
公开(公告)日：2018-01-17
申请号：EP16708032.4
申请日：2016-02-12
申请人： Qualcomm Incorporated
发明人： ARCUDIA, Kenneth Luis , SHAFER, Jeffrey Andrew , PANDITA, Bupesh
IPC分类号： H03L7/091 , H03L7/093
CPC分类号： H04L7/0332 , H03B5/1212 , H03B5/1228 , H03L7/091 , H03L7/093 , H04L7/0025 , H04L7/041
摘要： In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.

9. 发明公开

EP2959587A4 SINGLE INSERTION TRIMMING OF HIGHLY ACCURATE REFERENCE OSCILLATORS 有权转让
标题翻译：高精密基准震荡器一次性使用修剪
公开(公告)号：EP2959587A4
公开(公告)日：2017-04-19
申请号：EP14754237
申请日：2014-02-19
申请人： SI-WARE SYSTEMS
发明人： ELKHOLY AHMED , AHMED AYMAN
IPC分类号： H03L7/099 , H03L1/02 , H03L7/085 , H03L7/16
CPC分类号： H03L1/026 , H03L1/027 , H03L1/04 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/06 , H03L2207/50
摘要： A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilized to adjust the phase and frequency of the SCO to meet frequency stability versus temperature and frequency accuracy requirements for a reference clock. The techniques used in the SPT algorithm provide a robust, fast and low testing cost for the SCO. Moreover, the concepts and techniques utilized in the SCO SPT can be used effectively for any temperature compensated oscillator (TCO) including TCXO, MEMS, FBAR and RC oscillators. Additionally, the described SPT algorithm is capable of measuring the temperature sensitivity of any oscillator, estimating suitable temperature compensation parameters and adjusting the oscillator frequency to the required value simultaneously.

10. 发明公开

EP3138228A1 CLOCK AND DATA RECOVERY WITH HIGH JITTER TOLERANCE AND FAST PHASE LOCKING 审中-公开
标题翻译： TAKT- UNDDATENRÜCKGEWINNUNGMIT HOHER JITTER-TOLERANZ UND SCHNELLER PHASENREGELUNG
公开(公告)号：EP3138228A1
公开(公告)日：2017-03-08
申请号：EP15718283.3
申请日：2015-03-17
申请人： Qualcomm Incorporated
发明人： SONG, Yu , DIFFENDERFER, Jan Christian , CHEN, Nan , WEST, David Ian , VIANI, Paul Lawrence
IPC分类号： H04L7/033 , H03L7/08
CPC分类号： H04L7/0016 , H03L7/0807 , H03L7/091 , H04L7/0083 , H04L7/0338
摘要： Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
摘要翻译：公开了一种用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

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