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1. 发明授权

EP3912270B1 HIGH-ORDER PHASE TRACKING LOOP WITH SEGMENTED PROPORTIONAL AND INTEGRAL CONTROLS 有权
公开(公告)号：EP3912270B1
公开(公告)日：2024-08-21
申请号：EP20713463.6
申请日：2020-02-25
IPC分类号： H03L7/081 , H03L7/087 , H03L7/18
CPC分类号： H03J2200/1120130101 , H03L7/087 , H03L7/185 , H03L7/1976 , H03L7/235 , H03L7/081 , H03L7/18

2. 发明授权

EP3255453B1 SUBSAMPLING MOTION DETECTOR FOR DETECTING MOTION OF OBJECT UNDER MEASUREMENT 有权
公开(公告)号：EP3255453B1
公开(公告)日：2018-10-24
申请号：EP17174502.9
申请日：2017-06-06
申请人： RichWave Technology Corp.
发明人： Chen, Tse-Peng
IPC分类号： G01S13/56 , H03L7/091 , H03L7/087 , H03L7/093 , H03L7/24
CPC分类号： H03L7/06 , G01S13/56 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/24
摘要： A subsampling motion detector(100, 150, 200, 300) configured to detect motion information of an object (24) under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object (24). A controllable oscillator (18, 58) outputs an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator (18, 58) for controlling the controllable oscillator (18, 58) through injecting locking. The subsampling motion detector (100, 150, 200, 300) further includes a subsampling phase detector (SSPD) (12, 112, 202) generating a control signal according to the oscillation signal generated by the controllable oscillator (18, 58) and a reference frequency (fXTAL), the SSPD outputting the control signal to the controllable oscillator (18, 58) for controlling the controllable oscillator (18, 58), the oscillation signal of the controllable oscillator (18, 58) being locked to a multiple of the reference frequency (fXAL) and the control signal representing the motion information of the object (24).

3. 发明授权

EP3043477B1 APPARATUS AND METHODS FOR CLOCK AND DATA RECOVERY 有权
标题翻译：用于时钟和数据恢复的装置和方法
公开(公告)号：EP3043477B1
公开(公告)日：2018-04-04
申请号：EP16150636.5
申请日：2016-01-08
申请人： Analog Devices, Inc.
发明人： McCRACKEN, Stuart , KENNEY, John , TAM, Kimo
IPC分类号： H03L7/091 , H04L7/033 , H04L25/14
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H04L7/0008 , H04L7/002 , H04L7/0033 , H04L7/02 , H04L7/042 , H04L25/14
摘要： Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.

4. 发明授权

EP2897001B1 Multi-level/multi-threshold/multi-persistency GPS/GNSS atomic clock monitoring 有权
标题翻译：多级/多阈值/多持续性GPS / GNSS原子钟监测
公开(公告)号：EP2897001B1
公开(公告)日：2017-09-06
申请号：EP14198176.1
申请日：2014-12-16
申请人： The Boeing Company
发明人： Li, Rongsheng , Ghassemi, Kamran
IPC分类号： G04F5/14 , G01R23/00 , G01S19/37 , G04G7/00 , G01S19/02 , G01S19/20
CPC分类号： G01S19/20 , G01S19/02 , G01S19/235 , G01S19/40 , G01S19/42 , G04F5/14 , H03L7/087 , H03L7/0991 , H04L27/00
摘要： Methods and apparatus to monitor GPS/GNSS atomic clocks are disclosed. An example method includes establishing a measured difference between an atomic frequency standard (AFS) and a monitoring device. The method also includes modeling an estimated difference model between the AFS and the monitoring device, and computing a residual signal based on the measured difference and the estimated difference model. In addition, the method includes analyzing, by a first detector, the residual signal at multiple thresholds, each of the thresholds having a corresponding persistency defining the number of times a threshold is exceeded before one or more of a phase jump, a rate jump, or an acceleration error is indicated. Furthermore, the method includes analyzing, by a second detector, a parameter of the estimated difference model at multiple thresholds, each of the thresholds having a corresponding persistency defining the number of times a drift threshold is exceeded before a drift is indicated.
摘要翻译：公开了监测GPS / GNSS原子钟的方法和设备。一种示例方法包括建立原子频率标准（AFS）与监测设备之间的测量差异。该方法还包括对AFS和监测装置之间的估计的差异模型建模，并且基于测量的差异和估计的差异模型来计算残差信号。此外，该方法包括通过第一检测器在多个阈值处分析残差信号，每个阈值具有相应的持久性，该相应的持续性定义了在相位跳跃，速率跳跃等中的一个或多个之前超过阈值的次数。或指示加速度错误。此外，该方法包括通过第二检测器在多个阈值处分析估计的差异模型的参数，每个阈值具有对应的持续性，所述对应的持续性定义了在指示漂移之前超过漂移阈值的次数。

5. 发明公开

EP3125432A1 TIME-TO-DIGITAL CONVERTER AND FREQUENCY TRACKING DEVICE AND METHOD 审中-公开
标题翻译： ZEIT-DIGITAL-WANDLER UNDFREQUENZNACHFÜHRUNGSVORRICHTUNGSOWIE VERFAHREN
公开(公告)号：EP3125432A1
公开(公告)日：2017-02-01
申请号：EP14890063.2
申请日：2014-11-04
申请人： Huawei Technologies Co. Ltd.
发明人： ZHOU, Shenghua , SONG, Dongli
IPC分类号： H03L7/08
CPC分类号： G04F10/005 , H03L7/085 , H03L7/087 , H03L2207/50
摘要： Embodiments of the present invention provide a time-to-digital converter, where the time-to-digital converter includes a delay unit, a first sampling unit, and a second sampling unit. The delay unit is connected to the first sampling unit and is configured to receive a first clock signal and delay the first clock signal; the first sampling unit is configured to perform sampling on the first clock signal and generate a first phase signal, so that a first phase-locked module adjusts a frequency of the first clock signal; the delay unit is further connected to the second sampling unit and is configured to receive a frequency-adjusted first clock signal and delay the frequency-adjusted first clock signal; and the second sampling unit is configured to perform sampling on the frequency-adjusted first clock signal and generate a second phase signal, so that the first phase-locked module adjusts a phase of the first clock signal. The embodiments of the present invention further disclose a frequency tracking apparatus and method. By using the present invention, an effect of double-loop frequency tracking may be achieved by using one time-to-digital converter, and an occupied area of a double-loop frequency tracking system is reduced.
摘要翻译：本发明的实施例提供了一种时间 - 数字转换器，其中时间 - 数字转换器包括延迟单元，第一采样单元和第二采样单元。所述延迟单元连接到所述第一采样单元，并且被配置为接收第一时钟信号并延迟所述第一时钟信号; 第一采样单元被配置为对第一时钟信号执行采样并产生第一相位信号，使得第一锁相模块调整第一时钟信号的频率; 所述延迟单元进一步连接到所述第二采样单元，并且被配置为接收经频率调整的第一时钟信号并延迟所述经频率调整的第一时钟信号; 并且第二采样单元被配置为对经频率调整的第一时钟信号执行采样并产生第二相位信号，使得第一锁相模块调整第一时钟信号的相位。本发明的实施例还公开了一种频率跟踪装置和方法。通过使用本发明，可以通过使用一个时间 - 数字转换器来实现双回路频率跟踪的效果，并且减少了双回路频率跟踪系统的占用面积。

6. 发明公开

EP3100357A1 DOUBLE PHASE-LOCKED LOOP WITH FREQUENCY STABILIZATION 有权
标题翻译：具有稳频双锁相环
公开(公告)号：EP3100357A1
公开(公告)日：2016-12-07
申请号：EP15744089.2
申请日：2015-01-14
申请人： Microsemi Semiconductor ULC
发明人： MILIJEVIC, Slobodan
IPC分类号： H03L7/07 , H03L7/099 , H04L7/00
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0805 , H03L7/0807 , H03L7/0991 , H03L7/22
摘要： A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first second phase-locked loops to provide a common output. The double phase locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks

7. 发明公开

EP3043477A3 APPARATUS AND METHODS FOR CLOCK AND DATA RECOVERY 有权
标题翻译： VORRICHTUNGEN UND VERFAHREN ZUR TAKT- UNDDATENRÜCKGEWINNUNG
公开(公告)号：EP3043477A3
公开(公告)日：2016-08-24
申请号：EP16150636.5
申请日：2016-01-08
申请人： Analog Devices, Inc.
发明人： McCRACKEN, Stuart , KENNEY, John , TAM, Kimo
IPC分类号： H03L7/091 , H04L7/033 , H04L25/14
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H04L7/0008 , H04L7/002 , H04L7/0033 , H04L7/02 , H04L7/042 , H04L25/14
摘要： Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.
摘要翻译：本文提供了用于时钟和数据恢复（CDR）的装置和方法。在某些配置中，第一CDR电路从在第一通道上接收的第一输入数据流捕获数据和边缘样本。数据和边缘采样用于产生主相位信号，该主相位信号用于控制用于捕获数据样本的第一数据采样时钟信号的相位。此外，第一CDR电路基于随着时间的主相位信号的变化产生主相位误差信号，并将主相位误差信号转发到至少第二CDR电路。第二CDR电路处理主相位误差信号以产生用于控制用于从通过第二通道接收的第二输入数据流捕获数据样本的第二数据采样时钟信号的相位的从相信号。

8. 发明授权

EP2232708B1 DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
标题翻译：与数字转换器TORGESTEUERTEM TIME数字锁相环路
公开(公告)号：EP2232708B1
公开(公告)日：2015-08-12
申请号：EP08869551.5
申请日：2008-12-24
申请人： QUALCOMM Incorporated
发明人： SUN, Bo , SAHOTA, Gurkanwal Singh , YANG, Zixiang
IPC分类号： H03L7/08 , H03L7/087
CPC分类号： H03L7/0802 , H03L7/087

9. 发明公开

EP2183674A4 SERIAL TRANSCEIVER AND COMMUNICATION METHOD USED BY THE SERIAL TRANSCEIVER 有权
标题翻译：串行收发器和通信方法串行收发器
公开(公告)号：EP2183674A4
公开(公告)日：2015-06-24
申请号：EP08772568
申请日：2008-07-16
申请人： KOREAN UNIVERSITY INDUSTRY & ACADEMY COOPERATION FOUNDATION
发明人： KIM CHULWOO , JUNG INHWA
IPC分类号： G06F13/14 , H03L7/08 , H03L7/087 , H03L7/089 , H03L7/095 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/04
CPC分类号： G06F13/385 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/044
摘要： A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.

10. 发明授权

EP1737174B1 Transmitter circuit, receiver circuit, data transmitting method and system 有权
标题翻译：发射器电路，接待电路数据传输方法和系统
公开(公告)号：EP1737174B1
公开(公告)日：2015-05-27
申请号：EP05730375.2
申请日：2005-04-12
申请人： Thine Electronics, Inc.
发明人： OZAWA, Seiichi, Thine Electronics, Inc. , OKAMURA, Jun-ichi, Thine Electronics, Inc. , ISHIONE, Yohei, Thine Electronics, Inc. , MIURA, Satoshi, Thine Electronics, Inc.
IPC分类号： H04L25/49 , H03L7/087 , H03L7/091 , H03L7/113 , H04L7/033 , H04L25/45
CPC分类号： H04L7/033 , H03K7/10 , H03L7/087 , H03L7/091 , H03L7/113 , H04L25/45 , H04L25/4902

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