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1. 发明公开

EP4432565A2 HIGH-ORDER PHASE TRACKING LOOP WITH SEGMENTED PROPORTIONAL AND INTEGRAL CONTROLS 审中-实审
公开(公告)号：EP4432565A2
公开(公告)日：2024-09-18
申请号：EP24190984.5
申请日：2020-02-25
申请人： Ciena Corporation
发明人： AOUINI, Sadok , BEN-HAMIDA, Naim , CREASY, Timothy James , ABDO, Ahmad , PARVIZI, Mahdi , JAKOBER, Lukas
IPC分类号： H03L7/18
CPC分类号： H03J2200/1120130101 , H03L7/087 , H03L7/185 , H03L7/1976 , H03L7/235 , H03L7/081 , H03L7/18
摘要： A clock recovery circuit (900) is described herein comprising: a plurality of clock inputs (105, 185, 187) including a reference clock (105) and at least one other clock input (185, 187); a phase rotator (115) and an accumulator (165) configured to perform frequency tracking providing integral control of an output signal (180) that is a synchronized clock signal based on the reference clock (105), wherein the integral control is based on the at least one other clock input (185, 187), and a digital fine delay element (350) configured to perform phase tracking providing the proportional control of an output signal (180), wherein the proportional control is based on the at least one other clock input (185, 187).

2. 发明公开

EP4395179A1 ELECTRONIC DEVICE, OPERATING METHOD THEREOF, AND ELECTRONIC SYSTEM 审中-公开
公开(公告)号：EP4395179A1
公开(公告)日：2024-07-03
申请号：EP23212178.0
申请日：2023-11-27
申请人： Samsung Electronics Co., Ltd.
发明人： CHOI, Youngho , LIM, Donghyuk , KWON, Kibaek
IPC分类号： H03L7/087 , H03L7/091 , H03L7/093 , H04L7/033
CPC分类号： H03L7/0807 , H04L7/0331 , H03L2207/0620130101 , H03L7/087 , H03L7/093 , H03L2207/5020130101 , H03L7/091
摘要： An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

3. 发明授权

EP3291447B1 DIGITAL PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME 有权
公开(公告)号：EP3291447B1
公开(公告)日：2018-12-05
申请号：EP16186301.4
申请日：2016-08-30
申请人： Stichting IMEC Nederland
发明人： VAN DEN HEUVEL, Johannes Henricus Cornelus , LIU, Yao-Hong
IPC分类号： H03L7/085
CPC分类号： H03L7/087 , G04F10/005 , H03L7/085 , H03L7/091 , H03L7/1976 , H03L2207/50
摘要： The present disclosure relates to a Digital Phase Locked Loop, DPLL, (1) for phase locking an output signal (2) to a reference clock signal (3). The DPLL (1) comprises a phase detector (5) for detecting a phase error of a feedback signal (6) with respect to the reference clock signal (3). The DPLL (1) comprises a digitally controlled oscillator (7) for generating the output signal (2) based at least on a frequency control word (8) and at least one control signal (11, 13) representative of the phase error. The phase detector (5) comprises an integer circuit (9) for generating a first control signal (11) representative of an integer phase error. The phase detector (5) comprises a fractional circuit (12) comprising a Time-to-Digital Converter, TDC, (14) for processing the feedback signal (6) and a delayed reference clock signal (4). The fractional circuit (12) is provided for generating from the TDC output (15) a second control signal (13) representative of a fractional phase error. The DPLL (1) comprises an unwrapping unit (17) for unwrapping the TDC output (15).

4. 发明授权

EP2959588B1 PHASE LOCK LOOP LOCK INDICATOR 有权
公开(公告)号：EP2959588B1
公开(公告)日：2018-12-05
申请号：EP14711043.1
申请日：2014-02-24
申请人： Microchip Technology Incorporated
发明人： BUCH, Fredrik , ALBINA, Cristian , YUENYONGSGOOL, Yong
IPC分类号： H03L7/095 , H03L7/087 , H03L7/089
CPC分类号： H03L7/087 , H03K5/26 , H03L7/089 , H03L7/095 , H03L7/097
摘要： A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock.

5. 发明公开

EP3394985A1 PHASE LOCKED LOOP, PHASE LOCKED LOOP ARRANGEMENT, TRANSMITTER AND RECEIVER AND METHOD FOR PROVIDING AN OSCILLATOR SIGNAL 有权
公开(公告)号：EP3394985A1
公开(公告)日：2018-10-31
申请号：EP15823334.6
申请日：2015-12-22
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： SJÖLAND, Henrik , PÅHLSSON, Tony
IPC分类号： H03L7/087 , H03L7/089
CPC分类号： H03L7/087 , H03L7/0896 , H03L7/0898
摘要： A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

6. 发明授权

EP1816741B1 Phase detector 有权
公开(公告)号：EP1816741B1
公开(公告)日：2018-10-03
申请号：EP07108304.2
申请日：2001-07-02
申请人： Texas Instruments Incorporated
发明人： Staszewski, Robert B. , Leipold, Dirk
IPC分类号： H03D13/00 , H03L7/091 , H03L7/085
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/50
摘要： A digital fractional phase detector (200) is provided to realize a frequency synthesizer architecture (100) that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO (104) and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector (200) is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock (110) and a reference clock by using a time-to-digital converter (201) to express the time difference as a digital word for use by the frequency synthesizer.

7. 发明授权

EP3197056B1 PHASE LOCKED LOOP CIRCUITS 有权
公开(公告)号：EP3197056B1
公开(公告)日：2018-08-01
申请号：EP16152608.2
申请日：2016-01-25
申请人： NXP B.V.
发明人： Kianush, Kaveh , Pol, Evert-Jan , Gevel, Marcel VAN DE
IPC分类号： H03L7/087 , H03L7/089 , H03L7/10 , H04L7/033
CPC分类号： H03L7/089 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/0331
摘要： A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

8. 发明公开

EP3306882A1 RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：接收电路和半导体集成电路
公开(公告)号：EP3306882A1
公开(公告)日：2018-04-11
申请号：EP17190648.0
申请日：2017-09-12
申请人： Socionext Inc.
发明人： KUDO, Masahiro
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H04L7/0087 , H03L7/087 , H03L7/0891 , H04L7/0337 , H04L25/03019 , H04L25/4917
摘要： A reception circuit includes a determination circuit including comparator circuits configured to determinate a level of a received signal and a logic circuit configured to generate a digital signal based on outputs of the comparator circuits. The determination circuit is configured to determinate by a first number of the comparator circuits when the received signal is a first signal which is a multivalued signal and determinate by a second number of the comparator circuits, the second number being smaller than the first number, when the received signal is a second signal. The logic circuit is configured to operate as a decoder which decodes outputs of the comparator circuits and generates the digital signal when the received signal is the first signal, and operates as a selector which selects an output of the comparator circuit for generating the digital signal when the received signal is the second signal.
摘要翻译：接收电路包括确定电路，该确定电路包括被配置为确定接收信号的电平的比较器电路以及被配置为基于比较器电路的输出生成数字信号的逻辑电路。确定电路被配置为当接收到的信号是作为多值信号并由第二数量的比较器电路确定的第一信号时由第一数量的比较器电路确定，当第二数量小于第一数量时，确定电路接收到的信号是第二信号。逻辑电路被配置为作为解码器工作，该解码器解码比较器电路的输出，并且当接收到的信号是第一信号时产生数字信号，并且当作为选择器选择用于产生数字信号的比较器电路的输出接收到的信号是第二信号。

9. 发明公开

EP3217559A1 HIGH ORDER HYBRID PHASE LOCKED LOOP WITH DIGITAL SCHEME FOR JITTER SUPPRESSION 有权转让
标题翻译：用数字方案抑制抖动的高阶混合锁相环
公开(公告)号：EP3217559A1
公开(公告)日：2017-09-13
申请号：EP17160147.9
申请日：2017-03-09
申请人： Ciena Corporation
发明人： AOUINI, Sadok , BEN-HAMIDA, Naim , PARVIZI, Mahdi
IPC分类号： H03L7/087 , H03L7/095 , H03L7/081
CPC分类号： H04L7/0331 , H03L7/06 , H03L7/07 , H03L7/0802 , H03L7/0805 , H03L7/081 , H03L7/0814 , H03L7/085 , H03L7/087 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L7/1806 , H03L7/193 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/06 , H03L2207/50
摘要： A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.
摘要翻译：一种过滤噪音的方法。该方法可以包括从锁相环（PLL）设备获得输出信号。该方法可以包括使用数字相位检测器和输出信号来确定PLL设备产生的PLL错误量。该方法可以包括使用延迟元件和数字滤波器从输出信号中滤除PLL错误量的一部分，以响应于确定PLL设备产生的PLL错误量来产生滤波信号。

10. 发明授权

EP3070874B1 A SYSTEM FOR SYNCHRONIZING OSCILLATING SIGNALS AND A METHOD OF OPERATING THE SYSTEM 有权转让
标题翻译：一种同步振荡信号的系统和一种操作该系统的方法
公开(公告)号：EP3070874B1
公开(公告)日：2017-05-31
申请号：EP15159267.2
申请日：2015-03-16
申请人： Deutsches Elektronen-Synchrotron DESY
发明人： Jablonski, Szymon , Schlarb, Holger
IPC分类号： H04B10/00 , H04L7/00 , H03L7/087
CPC分类号： H04L7/0075 , H03L7/087 , H04L7/0008

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