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1. 发明公开

EP0049273A4 COMPLEMENTARY FIELD-EFFECT TRANSISTOR INTEGRATED CIRCUIT DEVICE. 失效
标题翻译：以集成电路为互补场效应晶体管。
公开(公告)号：EP0049273A4
公开(公告)日：1982-11-25
申请号：EP81901057
申请日：1981-03-20
申请人： WESTERN ELECTRIC CO
发明人： LEPSELTER MARTIN PAUL
IPC分类号： H01L27/08 , H01L27/092 , H01L29/47 , H01L29/78 , H01L29/872 , H01L27/04 , H01L29/56
CPC分类号： H01L27/0921

2. 发明公开

EP0465151A3 Semiconductor device with Shottky junction 失效
标题翻译：具有SHOTTKY JUNCTION的半导体器件
公开(公告)号：EP0465151A3
公开(公告)日：1993-05-12
申请号：EP91305868.1
申请日：1991-06-28
申请人： CANON KABUSHIKI KAISHA
发明人： Nakamura, Yoshio , Kikuchi, Shin , Nishimura, Shigeru
IPC分类号： H01L29/91 , H01L29/73 , H01L29/784 , H01L29/56 , H01L29/48 , H01L21/285 , H01L29/40
CPC分类号： H01L29/66166 , H01L21/28537 , H01L29/47 , H01L29/7308 , H01L29/7839 , H01L29/872
摘要： A semiconductor device having a Shottky junction comprises: a first semiconductor area composed of an n-type semiconductor; a second semiconductor area composed of an n-type semiconductor of a higher resistance than in said first semiconductor area; an insulation film provided adjacent to said second semiconductor area and having an aperture therein; an electrode area provided in said aperture; and a third semiconductor area composed of a p-type semiconductor provided at the junction between said insulation film and said electrode area. The electrode area is composed of a monocrystalline metal and constitutes a Shottky junction with said second semiconductor area.

3. 发明公开

EP0348916A2 MOSFET equivalent voltage drive semiconductor device 失效
标题翻译： Einem MOSFETäquivalenteHalbleitervorrichtung zur Spannungssteuerung。
公开(公告)号：EP0348916A2
公开(公告)日：1990-01-03
申请号：EP89111707.9
申请日：1989-06-27
申请人： NISSAN MOTOR CO., LTD.
发明人： Murakami, Yoshinori , Mihara, Teruyoshi
IPC分类号： H01L29/56 , H01L29/72 , H01L29/76 , H01L29/78
CPC分类号： H01L29/772 , H01L29/7391 , H01L29/7827 , H01L29/7839
摘要： A semiconductor device including a semiconductor substrate having a first conductivity type, in which a metal electrode is formed on the semiconductor substrate to form a Schottky junction therebetween, and a gate electrode is arranged adjacent to the Schottky junction via an insulating film.
摘要翻译：一种半导体器件，包括具有第一导电类型的半导体衬底，其中在半导体衬底上形成金属电极以形成肖特基结，并且栅电极经由绝缘膜与肖特基结相邻。

4. 发明公开

EP0017021A1 Verfahren zur Herstellung einer Halbleiteranordnung mit komplementären Transistoren 失效
标题翻译：一种用于生产具有互补晶体管的半导体装置的过程。
公开(公告)号：EP0017021A1
公开(公告)日：1980-10-15
申请号：EP80101236.0
申请日：1980-03-11
申请人： International Business Machines Corporation
发明人： De Bar, David E. , Hamaker, Raymond W. , Stephens, Geoffrey B.
IPC分类号： H01L29/72 , H01L29/08 , H01L29/40 , H01L29/52 , H01L29/56 , H01L27/08
CPC分类号： H01L29/7308 , H01L27/0826 , H01L29/47
摘要： Es wird ein hinsichtlich Herstellung und Betriebseigenschaften verbesserter Aufbau von Bipolartransistoren, vorzugsweise von vertikalen PNP-Transistoren, angegeben. Als Emitter wird dabei ein Schottky-Kontakt (72) vorgesehen, der auf einem jeweils zugehörigen Basisgebiet (59) mit relativ niedriger Dotierungskonzentration in Form einer Metallbelegung aufgebracht wird. Damit lassen sich vorteilhaft, z.B. in einem konventionellen NPN-Bipolarprozeß, komplementäre Bipolartransistoren (25, 27) mit hoher Pakkungsdichte und insbesondere verbesserten Eigenschaften der PNP-Transistoren (25) aufbauen.
摘要翻译： 1.一种制造具有互补晶体管的半导体装置的N型导电性，其中，在晶体管到离子注入步骤的掩埋P-掺杂区形成为PNP的集电区的硅半导体材料，在另一掺杂步骤的方法到达至表面并叠加在p型掺杂区的p掺杂区域形成：作为NPN的晶体管的n掺杂区的另外的掺杂步骤中的基极区，并且其中在所述NPN晶体管的基极区域中形成作为对发射极该晶体管的区域，并且其中的金属涂层的施加到表面上的PNP晶体管的肖特基势垒接触地形成的集电极区域：作为该晶体管的发射极，通过以下工艺步骤为特征：1）第一离子注入步骤，一个埋respectivement P-掺杂区（28”，34，36）在开采PNP晶体管的半导体材料确定性的一个区域的至少生成的，并且至少在一个REG 离子确定性开采NPN晶体管，一个形成所述PNP晶体管的（子）集电区（34），和NPN晶体管的另一个基极区域（36）（图 2B）。 B）在第二注入步骤，叠加在埋入P-掺杂区并到达直至表面中的每个区域中产生，一个形成集电极接触区域中的p型掺杂区域（28”，42，44）（42） NPN晶体管（图2C）。c）中在第三掺杂步骤中，优选在离子注入步骤的PNP晶体管，而另一个是辅助基极区域（44），具有N型导电性的基极接触区的掺杂剂的（50）的NPN晶体管的PNP晶体管和所述发射极区域（52）的产生（图2E）。D）通过施加高功函数金属，肖特基势垒接触（72）提供所述PNP晶体管的发射极形成的从超过所述PNP晶体管（图2F）的（亚）集电极区域（34）的基极区域（59）的集电极接触区域（42）间隔开。

5. 发明公开

EP0603102A2 Low-temperature MOSFET source drain structure with ultra-short channel 失效
标题翻译： Wiedertemperatur-MOSFET-Source / Drain-Struktur mit ultrakurzem Kanal。
公开(公告)号：EP0603102A2
公开(公告)日：1994-06-22
申请号：EP93480189.5
申请日：1993-11-19
申请人： International Business Machines Corporation
发明人： Subbanna, Seshadri
IPC分类号： H01L29/784 , H01L29/54 , H01L29/56 , H01L27/092
CPC分类号： H01L29/7839 , H01L29/1087 , H01L29/66636 , H01L29/66643
摘要： The field effect transistor FET (30) in accordance with the invention includes a substrate or layer (31) in which areas in which transistors are formed are separated by shallow isolation trenches (32) formed of an oxide or other insulative material. Metal source and drain deposits (33), preferably of tungsten, extend into the substrate or layer (31) for a distance beyond shallow junction structures (34), adjacent to the source and drain (33) and serving to connect the source and drain to the conduction channel of the FET which extends between them. Gate (35) of N+ polysilicon or polycide is insulated from the conduction channel by gate insulator (37), preferably formed of an oxide of the substrate material. Gate oxide (37) extends over the shallow junctions structure (34) between the metal source and drain deposits (33). Oxide gate sidewalls (38) cover the region between the gate edges and the edge of the metal source and drain deposits (33). The gate sidewalls (38) are also preferably covered with a thin (e.g. 40 nm) nitride spacer (39). Optionally, a cap of polycide or metal such as tungsten (particularly if polycide is used for the gate) can be provided on the gate. This ultra-short channel FET provides a combination of a shallow junction for injection of carriers into a conduction channel and a Schottky barrier below the shallow junction with a lowered barrier height to reduce the depletion region and punch-through effects. A preferred method of fabricating this structure which includes both etching and metal deposition selectively on only semiconductor material, thus allowing use of only a single patterning step with registration tolerances comparable to channel length while allowing extremely high integration density, is also disclosed herein.
摘要翻译：根据本发明的场效应晶体管FET（30）包括其中形成晶体管的区域被由氧化物或其它绝缘材料形成的浅隔离沟（32）分开的衬底或层（31）。优选钨的金属源极和漏极沉积物（33）延伸到衬底或层（31）中一段距离远离源极和漏极（33）的浅结结构（34）的距离，并用于连接源极和漏极到在它们之间延伸的FET的导通通道。 N +多晶硅或多晶硅化物的栅极（35）通过栅极绝缘体（37）与导电沟道绝缘，优选由衬底材料的氧化物形成。栅极氧化物（37）在金属源极和漏极沉积物（33）之间的浅结点结构（34）上延伸。氧化物栅极侧壁（38）覆盖栅极边缘与金属源和漏极沉积物（33）的边缘之间的区域。栅极侧壁（38）也优选用薄（例如40nm）氮化物间隔物（39）覆盖。任选地，可以在栅极上提供多晶硅或金属如钨（特别是如果多晶硅用于栅极）。该超短沟道FET提供了一个浅结的组合，用于将载流子注入到导电沟道中，并且在浅结点下方具有降低势垒高度的肖特基势垒，以减少耗尽区域和穿透效应。本文还公开了一种制造这种结构的优选方法，其包括仅在半导体材料上选择性地进行蚀刻和金属沉积，从而允许仅使用具有与沟道长度相当的对准公差的单一图案化步骤，同时允许极高的积分密度。

6. 发明公开

EP0465151A2 Semiconductor device with Shottky junction 失效
标题翻译： Halbleiteranordnung mit Shottky-übergang。
公开(公告)号：EP0465151A2
公开(公告)日：1992-01-08
申请号：EP91305868.1
申请日：1991-06-28
申请人： CANON KABUSHIKI KAISHA
发明人： Nakamura, Yoshio , Kikuchi, Shin , Nishimura, Shigeru
IPC分类号： H01L29/91 , H01L29/73 , H01L29/784 , H01L29/56 , H01L29/48 , H01L21/285 , H01L29/40
CPC分类号： H01L29/66166 , H01L21/28537 , H01L29/47 , H01L29/7308 , H01L29/7839 , H01L29/872
摘要： A semiconductor device having a Shottky junction comprises: a first semiconductor area composed of an n-type semiconductor; a second semiconductor area composed of an n-type semiconductor of a higher resistance than in said first semiconductor area; an insulation film provided adjacent to said second semiconductor area and having an aperture therein; an electrode area provided in said aperture; and a third semiconductor area composed of a p-type semiconductor provided at the junction between said insulation film and said electrode area.
The electrode area is composed of a monocrystalline metal and constitutes a Shottky junction with said second semiconductor area.
摘要翻译：具有肖特基结的半导体器件包括：由n型半导体构成的第一半导体区域; 由比所述第一半导体区域高的电阻的n型半导体构成的第二半导体区域; 设置在所述第二半导体区域附近并在其中具有孔的绝缘膜; 设置在所述孔中的电极区域; 以及由设置在所述绝缘膜和所述电极区域之间的接合处的p型半导体构成的第三半导体区域。电极区域由单晶金属构成，与所述第二半导体区域构成肖特基结。

7. 发明公开

EP0252173A1 Vertical field effect transistor 失效
标题翻译： Vertikaler Feldeffekttransistor。
公开(公告)号：EP0252173A1
公开(公告)日：1988-01-13
申请号：EP86109269.0
申请日：1986-07-07
申请人： AT&T Corp.
发明人： Hwang, James Cheng-Min
IPC分类号： H01L29/80 , H01L29/64 , H01L29/52 , H01L29/10 , H01L21/76 , H01L21/265 , H01L21/28 , H01L27/14 , H01L29/56
CPC分类号： H01L29/8083 , H01L29/8122
摘要： A vertical field effect transistor (FET) (e.g., 20) disclosed which has a relatively short channel length and which reduces parasitic capacitance without employing a mesa isolation technique. A short channel length is achieved as a consequence of the fact that the source electrode (e.g., 56) of the FET is used as an etching and shadow mask to form two gate electrodes (e.g., 62), on the opposite sides of the source electrode, which are aligned with the sides of the source electrode. Parasitic capacitance is reduced because two of the contact pads (e.g., 82 and 84) of the FET are formed on a region of the semiconductor body (de.g., 24) of the FET whose electrical resistivity has been increased through the implantation of appropriately chosen ions.
摘要翻译：公开了一种垂直场效应晶体管（FET）（例如20），其具有相对较短的沟道长度，并且在不采用台面隔离技术的情况下降低寄生电容。由于FET的源电极（例如56）用作蚀刻和阴影掩模以在源的相对侧上形成两个栅电极（例如62）的事实，实现了短沟道长度电极，其与源极的侧面对准。降低了寄生电容，因为FET的两个接触焊盘（例如，82和84）形成在FET的半导体主体的区域（例如，24）上，其电阻率通过植入适当选择的离子。

8. 发明公开

EP0161555A2 Thin film field effect transistor and method of making same 失效
标题翻译： Dünnfilm-Feldeffekttransistor和Verfahren zu seiner Herstellung。
公开(公告)号：EP0161555A2
公开(公告)日：1985-11-21
申请号：EP85105034.4
申请日：1985-04-25
申请人： ENERGY CONVERSION DEVICES, INC.
发明人： Ovshinsky, Stanford R. , Hudgens, Stephen J.
IPC分类号： H01L29/04 , H01L29/161 , H01L29/56 , H01L29/78 , H01L21/84 , H01L21/324 , H01L27/08 , H01L27/12
CPC分类号： H01L27/1214 , H01L21/324 , H01L29/04 , H01L29/161 , H01L29/66742 , H01L29/7839 , H01L29/78618 , H01L29/7866
摘要： @ There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.
摘要翻译：公开了一种薄膜场效应晶体管，其可以以快速切换速率操作，例如用于视频显示应用中。该晶体管包括硅半导体材料体，其具有比无定形材料更有序的结构，并且比单晶材料有序。晶体管的源极和漏极包括形成在硅半导体材料体上的整流触点。还公开了制造晶体管和利用该晶体管的电子可寻址阵列系统的方法。

9. 发明公开

EP0683530A3 Anode region of insulated gule bipolar andmethod of manufacturing the same 失效
标题翻译：绝缘胶双极的阳极区及其制造方法
公开(公告)号：EP0683530A3
公开(公告)日：1996-01-03
申请号：EP95112247.2
申请日：1989-11-07
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Hagino, Hiroyasu, c/o Mitsubishi Denki K.K.
IPC分类号： H01L29/72 , H01L29/08 , H01L29/56 , H01L21/331 , H01L27/06 , H01L29/06
CPC分类号： H01L29/66333 , H01L29/0834 , H01L29/7395 , H01L29/7839 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2924/13055 , H01L2924/00014 , H01L2924/00
摘要： The present invention is directed to a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a first conductivity type semiconductor substrate (31) with first and second major surfaces. A first region (32) of a second conductivity type is provided in a portion of the first major surface of the substrate (31). A second region (33) of the second conductivity type is located in a portion of the second major surface of the substrate (31). A third region (34) of the first conductivity type is provided in the second region (33). An insulation film (35) is located on the surface of the second region (33) and extends to cover portions of the surfaces of the substrate (31) and the third region (34), wherein the insulation film (35) is disposed at a position substantially corresponding to the first region (32). A control electrode (36) is disposed on the insulation film (35) and a first electrode is disposed on the second major surface and extends on the third region (34) and the second region (33). A second electrode (38) is disposed on the first major surface and extends on the first region (32) and on a fourth region (58) of the first conductivity type. The area of the fourth region (58) is smaller than that of the first region (32). Hence, it is possible to reduce a current flowing in a parasitic diode formed by the second region (33) and the semiconductor substrate (31). The semiconductor device is particularly suitable for high-frequency use.
摘要翻译：本发明涉及一种半导体器件及其制造方法。该半导体器件包括具有第一和第二主表面的第一导电类型半导体衬底（31）。第二导电类型的第一区域（32）设置在衬底（31）的第一主表面的一部分中。第二导电类型的第二区域（33）位于衬底（31）的第二主表面的一部分中。第一导电类型的第三区域（34）设置在第二区域（33）中。绝缘膜（35）位于第二区域（33）的表面上并延伸以覆盖基板（31）和第三区域（34）的表面的一部分，其中绝缘膜（35）设置在基本对应于第一区域（32）的位置。控制电极（36）设置在绝缘膜（35）上，并且第一电极设置在第二主表面上并且在第三区域（34）和第二区域（33）上延伸。第二电极（38）设置在第一主表面上并且在第一区域（32）上和第一导电类型的第四区域（58）上延伸。第四区域（58）的面积小于第一区域（32）的面积。因此，可以减小在由第二区域（33）和半导体衬底（31）形成的寄生二极管中流动的电流。该半导体器件特别适合于高频率使用。

10. 发明公开

EP0601823A1 Field effect transistor with integrated schottky diode clamp 失效
标题翻译： Feldeffekttransistor mit integrierter肖特基 - 克拉默二极管。
公开(公告)号：EP0601823A1
公开(公告)日：1994-06-15
申请号：EP93309789.1
申请日：1993-12-06
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Mistry, Kaizad R.
IPC分类号： H01L27/02 , H01L29/56
CPC分类号： H01L29/1087 , H01L21/28537 , H01L27/0255 , H01L29/7839
摘要： A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs. The clamping performed by the invention reduces wearout and other deleterious effects of excess voltage.
摘要翻译： MOSFET器件采用集成的肖特基二极管钳位源，连接在源极或漏极端子与散装端子之间。在说明性实施例中，在位于p型硅衬底中的n阱中形成一个或多个MOSFET。每个漏极由金属硅化物层的一部分下面的p +区形成。在一个实施例中，p +区域位于金属硅化物的边缘的下方; 在另一个实施例中，p +区域位于金属硅化物的相对边缘的下方，使得金属硅化物的一部分接触n-阱。每个源由金属硅化物层下面的p +区形成。每个栅极包括一层由金属硅化物层包覆的p +或n +多晶硅层，栅极通过一层氧化物与n阱分离。与p-n结二极管相比，集成肖特基二极管更有效地限制了施加到MOSFET的过电压。本发明的钳位减少了过电压的损耗和其他有害影响。

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