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1. 发明公开

EP3853905A1 HIGH-VOLTAGE SEMICONDUCTOR DEVICE WITH INCREASED BREAKDOWN VOLTAGE AND MANUFACTURING METHOD THEREOF 无效
公开(公告)号：EP3853905A1
公开(公告)日：2021-07-28
申请号：EP19917297.4
申请日：2019-02-28
申请人： Yangtze Memory Technologies Co., Ltd.
发明人： SUN, Chao
IPC分类号： H01L29/02

2. 发明公开

EP3586368A1 METHODS AND APPARATUS FOR VERTICALLY STACKED MULTICOLOR LIGHT-EMITTING DIODE (LED) DISPLAY 审中-公开
公开(公告)号：EP3586368A1
公开(公告)日：2020-01-01
申请号：EP18757001.5
申请日：2018-02-23
申请人： Massachusetts Institute of Technology (MIT)
发明人： LEE, Kyusang , KONG, Wei , KIM, Jeehwan
IPC分类号： H01L29/02 , H01L33/26 , H01L33/36 , B32B38/10 , G09G3/32

3. 发明公开

EP3326208A1 FIELD-PLATE STRUCTURES FOR SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：EP3326208A1
公开(公告)日：2018-05-30
申请号：EP16828376.0
申请日：2016-07-18
申请人： Cambridge Electronics, Inc. , Xia, Ling , Azize, Mohamed , Lu, Bin
发明人： XIA, Ling , AZIZE, Mohamed , LU, Bin
IPC分类号： H01L29/66 , H01L29/02 , H01L31/02
CPC分类号： H01L29/404 , H01L27/0629 , H01L28/40 , H01L28/60 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/454 , H01L29/475 , H01L29/66181 , H01L29/7786 , H01L29/861 , H01L29/94
摘要： Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

4. 发明授权

EP2116895B1 Laminated structure for an image display device 有权
标题翻译：的图像显示装置的层结构
公开(公告)号：EP2116895B1
公开(公告)日：2016-12-14
申请号：EP09251176.5
申请日：2009-04-24
申请人： Ricoh Company, Ltd.
发明人： Suzuki, Koei , Tano, Takanori , Onodera, Atsushi
IPC分类号： G02F1/1362 , H01L29/02 , H01L51/52 , H01L51/05
CPC分类号： H01L51/0023 , G02F1/1339 , G02F2202/28 , G02F2202/36 , H01L51/0022 , H01L51/0545 , H01L51/525

5. 发明公开

EP2591499A4 RADIATION-HARDENED ROIC WITH TDI CAPABILITY, MULTI-LAYER SENSOR CHIP ASSEMBLY AND METHOD FOR IMAGING 有权
标题翻译：辐射集成电路ELITE（ROIC），多层片状传感器成像布置和方法
公开(公告)号：EP2591499A4
公开(公告)日：2016-08-10
申请号：EP11803926
申请日：2011-05-04
申请人： RAYTHEON CO
发明人： PFLIBSEN KENT P , VANCE LEONARD D , MCCOMAS BRIAN K
IPC分类号： H01L21/70 , H01L21/8234 , H01L29/02 , H04N5/335 , H04N5/345 , H04N5/372 , H04N5/374
CPC分类号： H04N5/3743 , H01L27/14634 , H01L27/1485 , H01L27/14856 , H04N5/335 , H04N5/3454 , H04N5/37206

6. 发明授权

EP2717294B1 METHOD FOR MANUFACTURING BONDED WAFER 有权转让
标题翻译：用于生产结合晶片
公开(公告)号：EP2717294B1
公开(公告)日：2016-04-06
申请号：EP12792204.5
申请日：2012-04-25
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： AGA, Hiroji , YOKOKAWA, Isao , NOTO, Nobuhiko
IPC分类号： H01L21/02 , H01L21/265 , H01L27/12 , H01L21/762 , H01L21/687 , H01L29/02
CPC分类号： H01L29/02 , H01L21/265 , H01L21/26586 , H01L21/68764 , H01L21/68771 , H01L21/76254 , Y10S438/977

7. 发明公开

EP2756524A1 RESISTIVE SWITCHING DEVICES HAVING ALLOYED ELECTRODES AND METHODS OF FORMATION THEREOF 审中-公开
标题翻译：采用合金电极电阻配线设备
公开(公告)号：EP2756524A1
公开(公告)日：2014-07-23
申请号：EP12832202.1
申请日：2012-07-13
申请人： Adesto Technologies Corporation , Adesto Technologies France Sarl
发明人： LEE, Wei Ti , GOPALAN, Chakravarthy , MA, Yi , SHIELDS, Jeffrey , BLANCHARD, Philippe , JAMESON, John Ross , KOUSHAN, Foroozan Sarah , WANG, Janet , KELLAM, Mark
IPC分类号： H01L29/02
CPC分类号： H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： A resistive switching device comprises a bottom electrode (115), a switching layer (130) disposed over the bottom electrode (115), and a electrode (150) disposed over the switching layer (130). The top electrode (150) comprises an alloy of a memory metal and an alloying element. The top electrode (150) provides a source of the memory metal. The memory metal is configured to change a state of the switching layer (130).

8. 发明公开

EP2412015A1 FABRICATION AND STRUCTURE OF ASYMMETRIC FIELD-EFFECT TRANSISTORS USING L-SHAPED SPACERS 审中-公开
标题翻译：生产和非对称的场效应晶体管的施工具有L形间隔件
公开(公告)号：EP2412015A1
公开(公告)日：2012-02-01
申请号：EP10756492.4
申请日：2010-03-25
申请人： National Semiconductor Corporation
发明人： PARKER, D., Courtney , ARCHER, Donald, M. , BAHL, Sandeep, R. , BULUCEA, Constantin , FRENCH, William, D. , JOHNSON, Peter, B. , YANG, Jeng-Jiun
IPC分类号： H01L21/70 , H01L29/02 , H01L29/10
CPC分类号： H01L29/0847 , H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A gate electrode (302) of a field-effect transistor (102) is defined above, and vertically separated by a gate dielectric layer (300) from, a channel-zone portion (284) of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion (290) using the gate electrode as a dopant-blocking shield. A spacer (304T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (280M and 282M) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (304). Electrical contacts (310 and 312) are formed respectively to the source/drain portions.

9. 发明公开

EP2116895A2 Laminated structure and image display device 有权
标题翻译： Schichtstrukturfüreine Bildanzeigevorrichtung
公开(公告)号：EP2116895A2
公开(公告)日：2009-11-11
申请号：EP09251176.5
申请日：2009-04-24
申请人： Ricoh Company, Ltd.
发明人： Suzuki, Koei , Tano, Takanori , Onodera, Atsushi
IPC分类号： G02F1/1362 , H01L29/02
CPC分类号： H01L51/0023 , G02F1/1339 , G02F2202/28 , G02F2202/36 , H01L51/0022 , H01L51/0545 , H01L51/525
摘要： A laminated structure includes a wettability variable layer (12) formed on a substrate (11), including a material whose critical surface tension varies by receiving energy so that high and low surface energy regions are formed; a conductive layer (13) formed in one of the high surface energy regions; and an insulating layer (15) formed in such a manner as to cover the conductive layer (13), wherein another one of the high surface energy regions is formed in such a manner as to surround a periphery of a circuit formation region (16) in which a plurality of the conductive layers are formed; and the insulating layer is formed in such a manner as to also cover the other one of the high surface energy regions so that an adhesive guard ring region (17) is formed between the wettability variable layer and the insulating layer (15).
摘要翻译：层叠结构包括：形成在基板（11）上的润湿性变化层（12），其包括通过接收能量而临界表面张力变化的材料，从而形成高低表面能区域; 形成在所述高表面能区域之一中的导电层（13）以及以覆盖导电层（13）的方式形成的绝缘层（15），其中另一个高表面能区域以围绕电路形成区域（16）的周边的方式形成，其中形成多个导电层; 并且绝缘层形成为也覆盖高表面能区域中的另一个，使得在润湿性变化层和绝缘层（15）之间形成粘合剂保护环区域（17）。

10. 发明公开

EP1883949A1 METHOD FOR PREPARING NANOCRYSTALLINE SILICON IN SIO2 AND FREESTANDING SILICON NANOPARTICLES 有权转让
标题翻译：用于生产纳米晶硅SiO2和独立的硅纳米粒子
公开(公告)号：EP1883949A1
公开(公告)日：2008-02-06
申请号：EP06741561.2
申请日：2006-05-26
申请人： The Governors of the University of Alberta
发明人： VEINOT, Jonathan, Gordon, Conn , HESSEL, Colin, Michael
IPC分类号： H01L21/00 , B81C5/00 , H01L29/02 , H01L29/04 , H01L33/00
CPC分类号： H01L21/316 , B82Y10/00 , C01B33/021 , H01L21/02134 , H01L21/02282 , H01L21/02337 , H01L21/02532 , H01L21/02628 , H01L21/2022 , H01L21/3124 , Y10T428/24421 , Y10T428/31663
摘要： Methods for preparing nanocrystalline-Si/SiO2 composites by treating hydrogen silsesquioxane (HSQ) under reductive thermal curing conditions are described. Also described are methods of preparing silicon nanoparticles by acid etching the nanocrystalline-Si/SiO2 composites.

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