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1. 发明授权

EP1438667B1 SYSTEM AND METHOD FOR CACHING DRAM USING AN EGRESS BUFFER 有权
标题翻译：系统和方法缓存中存储DRAM单元输出缓冲区
公开(公告)号：EP1438667B1
公开(公告)日：2006-05-24
申请号：EP02789223.1
申请日：2002-10-18
申请人： SUN MICROSYSTEMS, INC.
发明人： KOHN, Leslie, D. , WONG, Michael, K.
IPC分类号： G06F13/00
CPC分类号： H04L47/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/1423 , G06F9/30007 , G06F9/30043 , G06F9/3851 , G06F9/3879 , G06F9/3891 , G06F11/108 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F13/1689 , G06F21/72 , G09G2352/00 , G09G2360/121 , G09G2370/022 , G09G2370/20 , G11C11/4074 , H04L29/06 , H04L45/745 , H04L47/2441 , H04L49/90 , H04L49/9057 , H04L49/9089 , H04L69/22 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, a method for efficiently classifying packets for a multi-processor/mutli-thread environment is provided. The method initiates with receiving a packet. Then, header information is extracted form the received packet. Next, a first hash value is calculated. Then, a field of interest in a lookup table is determined from the first hash value. Next, a second hash value is calculated. Then, the second hash value is compared to stored hash values in the field of interest of the lookup table to determine a match between the second hash value and one of the values in the field of interest of the lookup table. If there is a match, the received packet is transmitted to a processor corresponding to the one of the values in the row location of the lookup table. A network interface card and a system for efficiently classifying packets in a multicore/multithread environment are also provided.

2. 发明公开

EP1021879A4 FULL-DUPLEX COMMUNICATION PROCESSOR 审中-公开
标题翻译：全双工通信处理器
公开(公告)号：EP1021879A4
公开(公告)日：2006-04-12
申请号：EP98951937
申请日：1998-09-24
申请人： EMULEX DESIGN & MFG CORP
发明人： ROACH BRADLEY , FIACCO PETER , SCHERER GREG
IPC分类号： G06F13/10 , H04J1/16 , G06F13/12 , H04B1/44 , H04L12/28 , H04L12/56 , H04L29/06 , H04L29/10
CPC分类号： H04L49/901 , G06F13/124 , H04L12/2801 , H04L29/06 , H04L49/90 , H04L49/9089 , H04L69/12
摘要： A full duplex communication processor (20) simultaneously sends and receives frames of data and commands. Separate transmit (32) and receive (30) protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving the CPU (40) on a frame-by-frame basis.

3. 发明公开

EP1491995A2 first-in-first-out memory 有权
标题翻译：双端口功能单端口连接器
公开(公告)号：EP1491995A2
公开(公告)日：2004-12-29
申请号：EP04102921.6
申请日：2004-06-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Liu, Heyun H.
IPC分类号： G06F5/06 , G06F5/00
CPC分类号： G06F5/12 , G06F5/10 , G06F2205/108 , G06F2205/123 , H04L49/90 , H04L49/9089
摘要： A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for buffering communications within the line card (20). Each of the buffers (24T, 24R) operate in a dual-port fashion, receiving asynchronous read and write requests, for reading data words from and writing data words to the buffers (24T, 24R). The buffers (24T, 24R) each include a memory array (45) of conventional single port random access memory cells, for example static RAM cells. Clock cycles are assigned by the buffers (24T, 24R) as internal read and internal write cycles, in alternating fashion. A write buffer (42) receives input data words, and schedules a double-data-word write to the memory array (45) upon receiving a pair of input data words, in the next internal write cycle. A read request buffer (44) receives read strobes, or read enable signals, from a downstream function, and upon receiving two such strobes, schedules the read of a double-data-word from the memory array (45). By converting the asynchronous read and write requests into scheduled reads and writes, respectively, the buffers (24T, 24R) operate as dual-port FIFO buffers.
摘要翻译：存储器具有写入缓冲器（42），当写入缓冲器（42）在接收到一对输入数据字时调度对存储器阵列（45）的双数据字写入。读取请求缓冲器（44）接收读取选通信号，或读取使能信号，并从数组中读取双数据字的时间表。该内存分别通过将异步读取和写入请求转换为预定的读取和写入来作为双端口FIFO存储器。独立权利要求还包括以下内容：（A）一种用存储器电路（B）缓冲数据字的方法，网络节点用于控制通过通信设施发送和接收基于分组的数据。

4. 发明公开

EP1400075A2 METHOD AND APPARATUS FOR DYNAMICALLY CONTROLLING DATA FLOW ON A BI-DIRECTIONAL DATA BUS 审中-公开
标题翻译：用于数据的动态控制方法和装置流作用下的双向BUS
公开(公告)号：EP1400075A2
公开(公告)日：2004-03-24
申请号：EP02756109.1
申请日：2002-05-30
申请人： Celox Networks, Inc.
发明人： RYAN, Andrew C. , SCHMID, Otto A. , ROSSMILLER, Matthew D.
IPC分类号： H04L12/56
CPC分类号： H04L49/9089 , H04L49/10 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/901
摘要： Disclosed herein is a method and apparatus for dynamically controlling data flow on a bi-directional data bus (120). Windows of time on the bus are divided between input, output, and pointer transactions. The number of input transactions relative to the number of output transactions is dynamically determined as a function of an input/output bias factor. Input transactions are written to a plurality of input queues (IQs) over the bus. The IQ receiving an input transaction is selected at least in part according to the occupancies of the IQs relative to a threshold occupancy. The number of output transactions allocated to an OQ during a window is determined as a function of that OQ's occupancy. Pointer transactions comprise reading or writing two copies of the pertinent pointers to prevent pointer corruption resulting from simultaneous pointer read/write accesses.

5. 发明公开

EP1037424A1 Method and Bus Interface for linking a bus with an application device 有权
标题翻译： Verfahren und Busschnittstelle zur Verbindung eines Buses mit einer Anwendungsvorrichtung
公开(公告)号：EP1037424A1
公开(公告)日：2000-09-20
申请号：EP00103618.5
申请日：2000-02-21
申请人： DEUTSCHE THOMSON-BRANDT GMBH
发明人： Schweidler, Siegfried , Brune, Thomas
IPC分类号： H04L1/00 , H04L29/06
CPC分类号： H04L12/40058 , H04L1/0061 , H04L12/40071 , H04L49/90 , H04L49/9057 , H04L49/9084 , H04L49/9089
摘要： The IEEE1394 bus communication protocol has three layers:
physical layer, link layer, and transaction layer. A link layer IC implements the interface to an external application and prepares data for sending on the bus, or interprets incoming data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions including arbitration for sending data on the bus. According to the invention the capacity of the on-chip memory becomes assigned in a flexible way in order to be able to meet the requirements for any specific service. Further, the on-chip memory is prevented from storing data packets containing transmission errors by CRC checking on the fly header data and other data. This is performed for asynchronous data packets as well as isochronous data packets, and allows to have a minimum on-chip memory capacity only.
摘要翻译： IEEE1394总线通信协议有三层：物理层，链路层和事务层。链路层IC实现与外部应用的接口，并准备用于在总线上发送的数据，或解释来自IEEE1394总线的输入数据分组。物理层IC实现与总线的直接电连接，并控制许多功能，包括在总线上发送数据的仲裁。根据本发明，以灵活的方式分配片上存储器的容量，以便能够满足任何特定服务的要求。此外，片上存储器被防止通过对毛头数据和其他数据的CRC校验来存储包含传输错误的数据分组。这是针对异步数据包和同步数据包执行的，并且允许仅具有最小的片上存储器容量。

6. 发明授权

EP1776807B1 VERFAHREN UND VORRICHTUNG ZUM ZUGRIFF AUF DATEN EINES BOTSCHAFTSSPEICHERS EINES KOMMUNIKATIONSBAUSTEINS 失效
标题翻译：方法和装置消息存储器的通信模块的数据访问
公开(公告)号：EP1776807B1
公开(公告)日：2009-12-16
申请号：EP05760912.5
申请日：2005-06-29
申请人： ROBERT BOSCH GMBH
发明人： HARTWICH, Florian , HORST, Christian , BAILER, Franz
IPC分类号： H04L12/56
CPC分类号： H04L49/9089 , H04L49/90
摘要： The invention relates to a method and a device for accessing data of a message memory (300) of a communication component (100) by inputting data into or outputting data from the message memory (300). The message memory is linked with a buffer memory unit (201 and 202) and the data are transmitted to the message memory in a first direction of transmission and from the message memory in a second direction of transmission. The buffer memory unit comprises an input buffer memory (201) in the first direction of transmission and an output buffer memory (202) in the second direction of transmission. The input buffer memory and the output buffer memory each are divided up into a partial buffer memory (400, 701) and a shaded memory (401, 700) for the partial buffer memory. The inventive method is characterized by the following steps: input of data into the respective partial buffer memory, exchanging the access to partial buffer memory and shaded memory so that subsequent data can be input into the shaded memory while the input data are already output from the partial buffer memory in the designated direction of transmission.

7. 发明公开

EP1445929A1 Memory management for a digital subscriber line telecommunication device 审中-公开
标题翻译： Speicherverwaltungfüreine DSLTelekommunikationsgerät
公开(公告)号：EP1445929A1
公开(公告)日：2004-08-11
申请号：EP03290322.1
申请日：2003-02-10
申请人： ALCATEL
发明人： Van Hoogenbemt, Stefaan Margriet Albert
IPC分类号： H04M11/06 , H04L27/26
CPC分类号： H04L49/9089 , H04L5/06 , H04L5/143 , H04L49/90 , H04M11/062
摘要： A Digital Subscriber Line [DSL] telecommunication device comprising at least one common memory (CM) that is shared between circuits (FFT, Demapper) of the downstream path and corresponding circuits (Mapper, IFFT) of the upstream path. The shared or common memory (CM) advantageously replaces the known two distinct memories (DM, UM) generally used, one for the downstream path and the other for the upstream path. The single common memory (CM) is particularly adapted to Very High Speed Digital Subscriber Line [VDSL-, VDSL or VDSL+] devices where the two downstream frequency ranges (DF1, DF2) are separated by an upstream frequency range (UF1); and where a second upstream frequency range (UF2) may exist. The size of the common memory shared by the fourth circuits is slightly larger (2800 carriers of 16 bits) than one (2048 carriers of 16 bits) of the known two memories interfacing each only two circuits of a same path. However, the size of this common memory is smaller than the sum (2 x 2048 carriers of 16 bits) of these two distinct memories.
摘要翻译：数字用户线路ÄDSLÜ电信设备包括在下游路径的电路（FFT，解映射器）和上游路径的对应电路（Mapper，IFFT）之间共享的至少一个公共存储器（CM）。共享或公共存储器（CM）有利地替代通常使用的已知的两个不同存储器（DM，UM），一个用于下游路径，另一个用于上行路径。单个公共存储器（CM）特别适用于两个下行频率范围（DF1，DF2）被上游频率范围（UF1）隔开的超高速数字用户线路ÄVDSL-，VDSL或VDSL +Ü设备; 并且其中可存在第二上游频率范围（UF2）。所述第四电路共享的共用存储器的大小比已经连接到相同路径中的每个只有两个电路的已知两个存储器的一个（2048个16位载波）略大（28位的16位载波）。然而，这个公共存储器的大小小于这两个不同存储器的总和（2×2048个载波的16位）。

8. 发明公开

EP1086552A1 OPTIMIZING THE TRANSFER OF DATA PACKETS BETWEEN LANS 有权
标题翻译：优化网络间数据分组的传输
公开(公告)号：EP1086552A1
公开(公告)日：2001-03-28
申请号：EP99927458.2
申请日：1999-06-10
申请人： CABLETRON SYSTEMS, INC.
发明人： BAUMERT, Robert, J. , SEAMAN, Anthony, W. , STAVES, Sherre, M.
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/9047 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9057 , H04L49/9089
摘要： A switch apparatus (10) for optimizing the transfer of data packets between a plurality of local area networks (LANs (12, 14, 16)). Apparatus of the present invention are comprised of multiple controllers (23), e.g., a receive controller (24), and a transmit controller (25), which share common resources including a first memory (a packet memory (20)) which stores the data packets, a second memory (a descriptor memory (22)) which stores pointers to the stored data packets, and buffered data paths (preferably using FIFO buffers (178, 108)). The independent controllers (25, 24) operate essentially concurrently for most tasks while interleaving their use of the shared resources (20, 22). Consequently, embodiments of the present invention can simultaneously receive and transmit data across multiple LAN data ports (18a, 18b, 18N) (e.g., 28 Ethernet ports comprised of 10/100 and/or 10 Mbps ports).
摘要翻译：一种交换装置（10），用于优化多个局域网（LAN（12,14,16））之间的数据分组传输。本发明的设备包括共享公共资源的多个控制器（23），例如接收控制器（24）和传输控制器（25），所述公共资源包括第一存储器（分组存储器（20）），数据分组，存储指向所存储的数据分组的指针的第二存储器（描述符存储器（22））以及缓冲数据路径（优选地使用FIFO缓冲器（178,108））。独立控制器（25,24）基本上同时操作大多数任务，同时交错使用共享资源（20,22）。因此，本发明的实施例可以通过多个LAN数据端口（18a，18b，18N）（例如，由10/100和/或10Mbps端口组成的28个以太网端口）同时接收和发送数据。

9. 发明公开

EP1026593A1 Multi channel controller 审中-公开
标题翻译： Vielfachkanalsteuerung
公开(公告)号：EP1026593A1
公开(公告)日：2000-08-09
申请号：EP99102338.3
申请日：1999-02-06
申请人： MOTOROLA, INC.
发明人： Weitz, Eliezer , Yeivin, Yoram , Socoletzki, Yossi , Katz, Adi , Kurnick, Moti , Shalev, Avi , Hagai, Avi
IPC分类号： G06F13/12 , G06F13/40 , H04L29/06
CPC分类号： H04L49/9089 , G06F13/128 , G06F13/4018 , H04J3/1605 , H04L49/90 , H04L49/9078
摘要： A communication controller (111) for handling and processing data packets received from a large number of communication channels (181 - 188). The communication controller (111) comprising of: a processor (160) for processing data; a serial interface (28), coupled to the communication channels (181 - 188). a multi channel controller (100, 100') coupled to the serial interface (28) and the processor (160), for interfacing between the communication channels (181 - 188) and the processor (160). The communication channels (181 - 188) and the serial interface (28) send and receive data packets. The processor (160) sends, receives and processes data words. The multi channel controller (100) receives data packets from the serial interface (28), concatenates data packets and sends data words to the processor (160). The multi channel controller (100) receives data words from the processor (160), and transmits data packets to the serial interface (28).
摘要翻译：一种用于处理和处理从大量通信信道（181-1888）接收的数据分组的通信控制器（111）。通信控制器（111）包括：处理器（160），用于处理数据; 耦合到通信信道（181-1888）的串行接口（28）。耦合到串行接口（28）和处理器（160）的多通道控制器（100,100'），用于在通信通道（181-188）和处理器（160）之间进行接口。通信信道（181〜188）和串行接口（28）发送和接收数据包。处理器（160）发送，接收和处理数据字。多通道控制器（100）从串行接口（28）接收数据分组，连接数据分组并将数据字发送到处理器（160）。多通道控制器（100）从处理器（160）接收数据字，并将数据包发送到串行接口（28）。

10. 发明公开

EP1023668A2 COMMUNICATION PROCESSOR HAVING BUFFER LIST MODIFIER CONTROL BITS 审中-公开
标题翻译：具有缓冲器列表修改器控制位的通信处理器
公开(公告)号：EP1023668A2
公开(公告)日：2000-08-02
申请号：EP98949477.8
申请日：1998-09-24
申请人： Emulex Corporation
发明人： ROACH, Bradley , FIACCO, Peter , SCHERER, Greg , BERMAN, Stuart , DUCKMAN, David
IPC分类号： G06F13/38 , G06F15/17
CPC分类号： H04L49/9089 , H04L29/06 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9052 , H04L49/9094 , H04L69/12
摘要： A communication processor (22) sends and receives frames of data and commands. Transmit and receive protocol engine (32 and 30) is controlled by host driver software (38) which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.
摘要翻译：通信处理器（22）发送和接收数据和命令的帧。发送和接收协议引擎（32和30）由主机驱动软件（38）控制，主机驱动软件利用预定的位来指示哪一帧是一系列帧中的最后一帧。这些信息在发送之前会被放置在发送帧中。

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